Patents by Inventor Ho Min Son
Ho Min Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170304Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes treating modules having an opening for taking in and taking out a substrate and which are stacked on each other; and an air flow generating member for generating a downward airflow at each treating module, and wherein the air flow generating member includes: a pan unit configured to supply an air; a spray unit configured to be provided above the treating module and which sprays an air supplied from the pan unit; and an exhaust unit configured to exhaust an air sprayed by the spray unit to outside of the treating module.Type: ApplicationFiled: November 21, 2023Publication date: May 23, 2024Applicant: SEMES CO., LTD.Inventors: Ho Jong HWANG, Hyun Goo PARK, Hyo Won YANG, Ki-Moon KANG, Sang Min LEE, Se Hoon OH, Won Sik SON
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Patent number: 8497545Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: GrantFiled: January 7, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Patent number: 8431983Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.Type: GrantFiled: December 30, 2009Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Jung-Yoon Ko, Sang-Kyoung Lee, Ho-Min Son, Won-Jun Jang, Jung-Geun Jee
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Publication number: 20110101437Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Patent number: 7888204Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: GrantFiled: August 15, 2008Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Patent number: 7855117Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.Type: GrantFiled: October 31, 2006Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
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Publication number: 20100171166Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.Type: ApplicationFiled: December 30, 2009Publication date: July 8, 2010Inventors: Woong Lee, Jung-Yoon Ko, Sang-Kyoung Lee, Ho-Min Son, Won-Jun Jang, Jung-geun Jee
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Publication number: 20090108323Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: ApplicationFiled: August 15, 2008Publication date: April 30, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Publication number: 20080093657Abstract: A method of fabricating a nonvolatile memory device includes forming at least one insulating layer on at least one of a semiconductor substrate and a layer including a semi-conductive material, and performing a plasma process using fluorine on the semiconductor. In some cases, an interface between the insulating layer and the semiconductor substrate includes fluorine.Type: ApplicationFiled: January 16, 2007Publication date: April 24, 2008Inventors: Ho-Min Son, Yong-Woo Hyung, Won-Jun Jang, Jung-Geun Jee, Hyoeng-Ki Kim
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Publication number: 20080064171Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.Type: ApplicationFiled: October 31, 2006Publication date: March 13, 2008Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
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Publication number: 20080044981Abstract: Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask.Type: ApplicationFiled: June 27, 2007Publication date: February 21, 2008Inventors: Jung Geun Jee, Won-Jun Jang, Woong Lee, Ho-Min Son, Won-Jun Lee, Hyoeng-Ki Kim, Jung-Hyun Park
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Publication number: 20080014729Abstract: In a method of manufacturing a memory device, a tunnel insulation layer and a floating gate layer are formed on a semiconductor substrate. A top surface of the floating gate layer is converted into a first nitride layer by a first nitridation treatment process. The first nitride layer is converted into a first oxynitride layer by a radical oxidation process. A lower oxide layer is formed on the first oxynitride layer by an LPCVD process. A second nitride layer and an upper oxide layer are formed on the lower oxide layer. A conductive layer is formed on the upper oxide layer. Thus, a multi-layered dielectric layer including the first oxynitride layer, the lower oxide layer, the second nitride layer, the upper oxide layer and the densified second oxynitride layer may have an increased capacitance without having degenerated leakage current characteristics.Type: ApplicationFiled: June 20, 2007Publication date: January 17, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Jung-Geun Jee, Hyoeng-Ki Kim, Jung-Hyun Park, Ho-Min Son, Won-Jun Jang
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Publication number: 20080014753Abstract: In a method of manufacturing a semiconductor device, a polysilicon layer doped with impurities is formed on a front side and a backside of a substrate. An insulation layer is formed on the substrate having the polysilicon layer to cover the polysilicon layer on the backside of the substrate. The insulation layer on the front side of the substrate is partially etched to partially expose the front side of the substrate. An oxidation process using oxygen radicals is then carried out to form an oxide layer on the exposed front side of the substrate Thus, when the oxidation process is carried out, the insulation layer prevents impurities in the polysilicon layer on the backside of the substrate from being outgassed. As a result electrical characteristics of the transistor formed on the front side of the substrate may not be deteriorated.Type: ApplicationFiled: May 3, 2007Publication date: January 17, 2008Inventors: Won-Jun Jang, Yong-Woo Hyung, Jae-Jong Han, Ho-Min Son, Woong Lee, Jung-Geun Jee
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Patent number: 7179707Abstract: A method for forming a gate electrode in the semiconductor device is disclosed. The disclosed methods for forming a gate electrode in a semiconductor includes forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the disclosed methods, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten suicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.Type: GrantFiled: November 26, 2003Date of Patent: February 20, 2007Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Ho Min Son
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Patent number: 7037785Abstract: Disclosed is a method of manufacturing the flash memory device.Type: GrantFiled: July 14, 2003Date of Patent: May 2, 2006Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Ho Min Son
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Patent number: 7030036Abstract: Provided is related to a method of forming an oxide layer of a semiconductor device. In the method, a first oxide layer is formed with a first thickness on a semiconductor substrate, that is comparted into first and second fields, and then a second oxide layer is formed on the first field with a second thickness, while preventing damages on the surface of the semiconductor substrate, after removing the first oxide layer on the first field. By the method, oxide layers different in thickness can be formed in separate field on the semiconductor substrate, without damages due to an etching process while enhancing the physical quality of the oxide layers.Type: GrantFiled: June 29, 2004Date of Patent: April 18, 2006Assignee: Hynix Semiconductor Inc.Inventor: Ho Min Son
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Publication number: 20040259369Abstract: A method for forming a gate electrode in the semiconductor device is disclosed. The disclosed methods for forming a gate electrode in a semiconductor includes forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the disclosed methods, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten suicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.Type: ApplicationFiled: November 26, 2003Publication date: December 23, 2004Inventors: Cha Deok Dong, Ho Min Son
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Publication number: 20040126972Abstract: Disclosed is a method of manufacturing the flash memory device.Type: ApplicationFiled: July 14, 2003Publication date: July 1, 2004Applicant: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Ho Min Son