Abstract: A semiconductor device includes a substrate having a semiconductor layer. A trench is formed within the semiconductor layer. A filling insulating film is disposed within the trench. An insertion liner is disposed within the filling insulating film. The insertion liner is spaced apart from the semiconductor layer and extends along the bottom surface of the trench.

Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.

Abstract: A semiconductor device includes a substrate having a semiconductor layer. A trench is formed within the semiconductor layer. A filling insulating film is disposed within the trench. An insertion liner is disposed within the filling insulating film. The insertion liner is spaced apart from the semiconductor layer and extends along the bottom surface of the trench.

Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.

Abstract: Embodiments of the present invention provide methods for forming a hardened and roughened ceramic component. Specific steps include forming a sintered ceramic component, texturing the surface of the sintered ceramic component, and firing the component to harden it. The resulting ceramic component may have a textured surface, and in a specific embodiment, the textured surface has a roughness of about 100 to about 2000 ?in Ra.

Abstract: According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

Abstract: A method of improving the adhesion of processing materials on a ceramic component is described. The method includes the steps of forming a green ceramic component and texturing the surface of the green ceramic component. The as-textured component is then fired to harden the ceramic material. In an alternative embodiment of the method, a coating is applied to the surface of the as-fired ceramic component to provide a secondary adhesion layer. A ceramic component for use in an etching or deposition reactor chamber is also described. The ceramic component includes a substrate formed of a ceramic material and has a textured surface formed thereon such that the textured surface has a roughness of about 100 to 1000 ?in Ra.

Abstract: According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

Abstract: According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

Abstract: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

Abstract: According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

Abstract: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.