Patents by Inventor Ho-Tai Chen
Ho-Tai Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049958Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.Type: GrantFiled: July 8, 2019Date of Patent: June 29, 2021Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.Inventors: Sung-Nien Tang, Ho-Tai Chen, Hsiu-Wen Hsu
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Publication number: 20200027968Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.Type: ApplicationFiled: July 8, 2019Publication date: January 23, 2020Inventors: SUNG-NIEN TANG, HO-TAI CHEN, HSIU-WEN HSU
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Patent number: 10014369Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.Type: GrantFiled: February 1, 2017Date of Patent: July 3, 2018Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.Inventors: Sung-Nien Tang, Ho-Tai Chen, Hsiu-Wen Hsu
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Publication number: 20170309705Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.Type: ApplicationFiled: February 1, 2017Publication date: October 26, 2017Inventors: SUNG-NIEN TANG, HO-TAI CHEN, HSIU-WEN HSU
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Patent number: 8319284Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.Type: GrantFiled: July 20, 2010Date of Patent: November 27, 2012Assignee: Sinopower Semiconductor Inc.Inventors: Wei-Chieh Lin, Ho-Tai Chen, Jia-Fu Lin, Po-Hsien Li
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Patent number: 8241978Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.Type: GrantFiled: August 6, 2009Date of Patent: August 14, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
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Patent number: 8242537Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.Type: GrantFiled: November 10, 2009Date of Patent: August 14, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Jen-Hao Yeh, Ho-Tai Chen
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Patent number: 8168480Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.Type: GrantFiled: September 21, 2009Date of Patent: May 1, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Ho-Tai Chen, Jen-Hao Yeh, Li-Cheng Lin, Shih-Chieh Hung
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Publication number: 20110278671Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.Type: ApplicationFiled: July 20, 2010Publication date: November 17, 2011Inventors: Wei-Chieh Lin, Ho-Tai Chen, Jia-Fu Lin, Po-Hsien Li
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Patent number: 8049273Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.Type: GrantFiled: February 15, 2009Date of Patent: November 1, 2011Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Ho-Tai Chen, Li-Cheng Lin, Jen-Hao Yeh, Hsin-Yen Chiu, Hsin-Yu Hsu, Shih-Chieh Hung
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Publication number: 20110079819Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.Type: ApplicationFiled: November 10, 2009Publication date: April 7, 2011Inventors: Wei-Chieh Lin, Jen-Hao Yeh, Ho-Tai Chen
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Publication number: 20100301386Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.Type: ApplicationFiled: September 21, 2009Publication date: December 2, 2010Inventors: Wei-Chieh Lin, Ho-Tai Chen, Jen-Hao Yeh, Li-Cheng Lin, Shih-Chieh Hung
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Publication number: 20100289075Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.Type: ApplicationFiled: August 6, 2009Publication date: November 18, 2010Inventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
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Publication number: 20100117142Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.Type: ApplicationFiled: February 15, 2009Publication date: May 13, 2010Inventors: Wei-Chieh Lin, Ho-Tai Chen, Li-Cheng Lin, Jen-Hao Yeh, Hsin-Yen Chiu, Hsin-Yu Hsu, Shih-Chieh Hung
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Publication number: 20100117164Abstract: A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region.Type: ApplicationFiled: April 20, 2009Publication date: May 13, 2010Inventors: Wei-Chieh Lin, Ho-Tai Chen, Hsin-Yu Hsu
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Patent number: 7682903Abstract: A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.Type: GrantFiled: December 14, 2008Date of Patent: March 23, 2010Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Hsin-Yu Hsu, Hsin-Yen Chiu, Shih-Chieh Hung, Ho-Tai Chen, Jen-Hao Yeh, Li-Cheng Lin
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Publication number: 20100055857Abstract: A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.Type: ApplicationFiled: December 14, 2008Publication date: March 4, 2010Inventors: Wei-Chieh Lin, Hsin-Yu Hsu, Hsin-Yen Chiu, Shih-Chieh Hung, Ho-Tai Chen, Jen-Hao Yeh, Li-Cheng Lin