Patents by Inventor Hohyun Shin
Hohyun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012712Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.Type: ApplicationFiled: February 15, 2023Publication date: January 11, 2024Inventors: Jongcheol Kim, Hyunsung Shin, Hohyun Shin, Taeyoung Oh, Kyungsoo Ha
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Publication number: 20230410925Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Inventors: Minho Choi, Jaeseong Lim, Kyungryun Kim, Daehyun Kim, Wonil Bae, Hohyun Shin, Sanghoon Jung, Hyongryol Hwang
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Patent number: 11776644Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.Type: GrantFiled: February 3, 2022Date of Patent: October 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Minho Choi, Jaeseong Lim, Kyungryun Kim, Daehyun Kim, Wonil Bae, Hohyun Shin, Sanghoon Jung, Hyongryol Hwang
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Patent number: 11450396Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.Type: GrantFiled: August 10, 2021Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
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Publication number: 20220284975Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.Type: ApplicationFiled: February 3, 2022Publication date: September 8, 2022Inventors: Minho Choi, Jaeseong Lim, Kyungryun Kim, Daehyun Kim, Wonil Bae, Hohyun Shin, Sanghoon Jung, Hyongryol Hwang
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Patent number: 11334457Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.Type: GrantFiled: April 3, 2020Date of Patent: May 17, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hohyun Shin, Jongwan Kim, Hyungi Kim, Hyunsung Shin, Dongmin Kim, Myeongo Kim, Kwangil Park, Youngsoo Sohn
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Publication number: 20220020445Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.Type: ApplicationFiled: August 10, 2021Publication date: January 20, 2022Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
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Patent number: 11094390Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.Type: GrantFiled: February 20, 2020Date of Patent: August 17, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
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Publication number: 20210012849Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.Type: ApplicationFiled: February 20, 2020Publication date: January 14, 2021Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee