Patents by Inventor Hoichi Cheong
Hoichi Cheong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9710277Abstract: A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.Type: GrantFiled: September 24, 2010Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Venkateswara R. Madduri, Jonathan Y. Tong, Hoichi Cheong
-
Patent number: 8930678Abstract: Techniques to increase the consumption rate of raw instruction bytes within an instruction fetch unit. An instruction fetch unit according to embodiments of the present invention may include a prefetch buffer, a set of bypass multiplexers, an array of bypass latches, a byte-block multiplexer, an instruction alignment multiplexer, a predecode cache, and an instruction length decoder. Raw instruction bytes may be steered from the bypass latches into macro-instructions for consumption by the instruction length decoder, which may generate micro-instructions from the macro-instructions. Embodiments of the present invention may de-couple a latency for reading raw instruction bytes from the prefetch buffer from consuming raw instruction bytes by the instruction length decoder.Type: GrantFiled: April 26, 2012Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Venkateswara R. Madduri, Hoichi Cheong, Jonathan Y. Tong
-
Publication number: 20130290678Abstract: Techniques to increase the consumption rate of raw instruction bytes within an instruction fetch unit. An instruction fetch unit according to embodiments of the present invention may include a prefetch buffer, a set of bypass multiplexers, an array of bypass latches, a byte-block multiplexer, an instruction alignment multiplexer, a predecode cache, and an instruction length decoder. Raw instruction bytes may be steered from the bypass latches into macro-instructions for consumption by the instruction length decoder, which may generate micro-instructions from the macro-instructions. Embodiments of the present invention may de-couple a latency for reading raw instruction bytes from the prefetch buffer from consuming raw instruction bytes by the instruction length decoder.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Applicant: INTEL CORPORATIONInventors: Venkateswara R. MADDURI, Hoichi CHEONG, Jonathan Y. TONG
-
Publication number: 20120079242Abstract: A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Venkateswara R. Madduri, Jonathan Y. Tong, Hoichi Cheong
-
Patent number: 7783871Abstract: According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.Type: GrantFiled: June 30, 2003Date of Patent: August 24, 2010Assignee: Intel CorporationInventors: Jonathan D. Combs, Hoichi Cheong
-
Patent number: 7266648Abstract: A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.Type: GrantFiled: August 29, 2005Date of Patent: September 4, 2007Assignee: Intel CorporationInventors: Edwin R. Sutanto, Hoichi Cheong, Zhongru J. Lin, Jeffrey L. Nye
-
Patent number: 7080241Abstract: An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instruction should be selectable for issuing as soon as its source operands are available. An instruction in the issue queue having source operands depending on other, target, instructions to determine their value are signaled to the target instruction by a link mask in the queue entry corresponding to the target instruction. A bit in the link mask identifies the queue entry corresponding to the dependent instruction. When the target instruction issues to the execution unit, a bit is set in a predetermined portion of the queue entry containing the dependent instruction. The portion of the queue entry is associated with the source operand depending on the issuing instruction.Type: GrantFiled: July 11, 2001Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Hung Qui Le, Hoichi Cheong
-
Publication number: 20060064551Abstract: A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.Type: ApplicationFiled: August 29, 2005Publication date: March 23, 2006Inventors: Edwin Sutanto, Hoichi Cheong, Zhongru Lin, Jeffrey Nye
-
Patent number: 6986010Abstract: A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.Type: GrantFiled: December 13, 2002Date of Patent: January 10, 2006Assignee: Intel CorporationInventors: Edwin R. Sutanto, Hoichi Cheong, Zhongru J. Lin, Jeffrey L. Nye
-
Patent number: 6898696Abstract: A method and system for increasing the efficiency of execution in a processor. Instructions are dispatched in instruction groups, wherein if such an instruction group contains an interruptible instruction of a selected type, only one interruptible instruction of the selected type is included in the instruction group. A state of the processor is recorded, associated respectively with each of said dispatched instruction groups. The processor is restored to the recorded state associated with the instruction group containing the interruptible instruction of the selected type causing an interrupt, in response to the interrupt from one of the interruptible instructions of the selected type.Type: GrantFiled: June 14, 1999Date of Patent: May 24, 2005Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Hung Qui Le
-
Publication number: 20040268102Abstract: According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Jonathan D. Combs, Hoichi Cheong
-
Publication number: 20040117573Abstract: A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Inventors: Edwin R. Sutanto, Hoichi Cheong, Zhongru J. Lin, Jeffrey L. Nye
-
Patent number: 6604173Abstract: A method for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, the method includes determining a smallest cache memory size for use in the at least one external cache memory, and configuring a tag array of the at least one external cache memory to support the smallest determined cache memory size. A system for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, includes a circuit for configuring each tag field of a plurality of tag fields in a tag array in the at least one external cache memory to have a number of bits sufficient to support a smallest determined cache memory, and utilizing each tag field to determine whether data being accessed resides in the at least one external cache memory.Type: GrantFiled: November 21, 1995Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Dwain A. Hicks, George M. Lattimore, Peichun P. Liu
-
Patent number: 6553480Abstract: A group completion table (GCT) that manages the execution of instruction groups having more than one executable instruction is disclosed. The GCT includes a plurality of table entries, wherein each of the table entries is associated with a respective instruction group. Each table entry in the GCT includes a plurality of instruction completion identifiers, wherein each of the instruction completion identifiers corresponds to a specific instruction in the associated instruction group. The table entry also includes a trouble identifier that is utilized to flag the occurrence of any exception condition encountered in the execution of any instruction in the instruction group. In a related embodiment, the trouble identifier utilized in the table entry is a single bit.Type: GrantFiled: November 5, 1999Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Hung Qui Le
-
Patent number: 6535973Abstract: A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.Type: GrantFiled: August 26, 1999Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Maureen A. Delaney, Hung Qui Le, Robert McDonald, Dung Quoc Nguyen, David Wayne Victor
-
Patent number: 6473850Abstract: An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.Type: GrantFiled: September 2, 1999Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: Hoichi Cheong, R. William Hay, James Allan Kahle, Hung Qui Le
-
Patent number: 6324640Abstract: Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of these instructions within the multiple groups. The renaming mechanism includes a rename table allocated for each dispatched group. A delay register is implemented between a portion of the dispatch queue dispatching a second one of the groups of instructions and a second one of the rename tables.Type: GrantFiled: June 30, 1998Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Hung Qui Le, Hoichi Cheong
-
Publication number: 20010042192Abstract: An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instruction should be selectable for issuing as soon as its source operands are available. An instruction in the issue queue having source operands depending on other, target, instructions to determine their value are signaled to the target instruction by a link mask in the queue entry corresponding to the target instruction. A bit in the link mask identifies the queue entry corresponding to the dependent instruction. When the target instruction issues to the execution unit, a bit is set in a predetermined portion of the queue entry containing the dependent instruction. The portion of the queue entry is associated with the source operand depending on the issuing instruction.Type: ApplicationFiled: July 11, 2001Publication date: November 15, 2001Inventors: Hung Qui Le, Hoichi Cheong
-
Patent number: 6308260Abstract: An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instruction should be selectable for issuing as soon as its source operands are available. An instruction in the issue queue having source operands depending on other, target, instructions to determine their value are signaled to the target instruction by a link mask in the queue entry corresponding to the target instruction. A bit in the link mask identifies the queue entry corresponding to the dependent instruction. When the target instruction issues to the execution unit, a bit is set in a predetermined portion of the queue entry containing the dependent instruction. The portion of the queue entry is associated with the source operand depending on the issuing instruction.Type: GrantFiled: September 17, 1998Date of Patent: October 23, 2001Assignee: International Business Machines CorporationInventors: Hung Qui Le, Hoichi Cheong
-
Patent number: 6098167Abstract: In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.Type: GrantFiled: March 31, 1997Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Hung Qui Le, John Stephen Muhich, Steven Wayne White