Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: A transceiver module includes a protocol converter for converting between the data protocol of a host and a network. In one embodiment the module performs protocol conversion between a TDM data protocol of an external network and a gigabit Ethernet data protocol of host, thereby eliminating the need for additional line cards to perform protocol conversion.

Abstract: A bit stuffing circuit has a first communication channel delivering data to a barrel shifter, the barrel shifter delivering a first number of bits from the first communication channel to a first output. A second output has a predetermined number of bits for transmission, the predetermined number of bits including the first number of bits from the barrel shifter output, and a second number of other bits from a second communications channel.

Abstract: A method of generating timing signals for constant bit rate data received over an asynchronous data network carrying, comprises recovering clock signals from at least two separate sources, selecting one of the sources to drive a phase-locked loop generating a high speed output signal locked to the selected source, dividing the high speed output signal to provide the required timing signals for said constant bit rate data, and continually monitoring the selected source. In the event of failure of the selected source, the phase-locked loop is allowed to free run in a hold-over mode while it is switched over to the other source.

Abstract: A method of controlling the supply of cells into an asynchronous network, comprises the steps of storing incoming bytes from multiple channels in respective channel buffers, creating in memory a timing event wheel partitioned into a plurality of sectors, of which one is active at any time, and placing cell pointers in the sectors. The cell pointers identify channel buffers and are distributed around the wheel in accordance with a desired transmission schedule. The wheel is stepwise advanced at a predetermined rate, and the cell pointers in the active sector are scanned at each advance of the wheel to identify the corresponding channel buffers. The bytes from the identified channel buffers are assembled into cells, which are forwarded for transmission over the asynchronous network. These are then multiplexed with VBR cells from another source.

Abstract: A data segmentation circuit is disclosed for use in DS3/STS-1 mapping. The data segmentation circuit uses a circular data buffer to store data for mapping. A recirculating barrel shifter is used for extracting data from within the buffer. A counter moves the barrel shifter window zero, one, five, or eight bits to align the barrel shifter output as necessary to extract a next datum for a next payload envelope location. Data stuffing is then performed. Control circuitry for providing throttling and bit stuffiing as required in an STS-1 information payload is disclosed.

Abstract: A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns.