Patents by Inventor Holger Huesken
Holger Huesken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11532508Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.Type: GrantFiled: February 25, 2021Date of Patent: December 20, 2022Assignee: Infineon Technologies AGInventors: Holger Huesken, Frank Dieter Pfirsch
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Publication number: 20210202304Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.Type: ApplicationFiled: February 25, 2021Publication date: July 1, 2021Inventors: Holger Huesken, Frank Dieter Pfirsch
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Patent number: 10998399Abstract: A power semiconductor device includes a semiconductor substrate with an edge termination region between an active region and a lateral rim. Non-metallic electrodes extend in the edge termination region on a front side of the substrate, and include at least three spaced apart non-metallic electrodes. One non-metallic electrode is an inner non-metallic electrode having an inner edge. Another non-metallic electrode is an outer non-metallic electrode having an outer edge. The shortest distance between the inner edge of the inner non-metallic electrode and the outer edge of the most non-metallic electrode is defined as distance p. Each non-metallic electrode is electrically connected to a respective doping region of the substrate by at least two respective metallic plugs each extending through a respective first opening formed in an electrically insulating bottom layer. The shortest distance d between any two metallic plugs of different non-metallic electrodes is larger than the distance p.Type: GrantFiled: June 28, 2019Date of Patent: May 4, 2021Assignee: Infineon Technologies AGInventors: Alice Pei-Shan Hsieh, Philip Christoph Brandt, Holger Huesken, Viktoryia Lapidus, Manfred Pfaffenlehner, Frank Dieter Pfirsch
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Patent number: 10950494Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.Type: GrantFiled: January 18, 2019Date of Patent: March 16, 2021Assignee: Infineon Technologies AGInventors: Holger Huesken, Frank Dieter Pfirsch
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Publication number: 20200013854Abstract: A power semiconductor device includes a semiconductor substrate with an edge termination region between an active region and a lateral rim. Non-metallic electrodes extend in the edge termination region on a front side of the substrate, and include at least three spaced apart non-metallic electrodes. One non-metallic electrode is an inner non-metallic electrode having an inner edge. Another non-metallic electrode is an outer non-metallic electrode having an outer edge. The shortest distance between the inner edge of the inner non-metallic electrode and the outer edge of the most non-metallic electrode is defined as distance p. Each non-metallic electrode is electrically connected to a respective doping region of the substrate by at least two respective metallic plugs each extending through a respective first opening formed in an electrically insulating bottom layer. The shortest distance d between any two metallic plugs of different non-metallic electrodes is larger than the distance p.Type: ApplicationFiled: June 28, 2019Publication date: January 9, 2020Inventors: Alice Pei-Shan Hsieh, Philip Christoph Brandt, Holger Huesken, Viktoryia Lapidus, Manfred Pfaffenlehner, Frank Dieter Pfirsch
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Publication number: 20190229013Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.Type: ApplicationFiled: January 18, 2019Publication date: July 25, 2019Inventors: Holger Huesken, Frank Dieter Pfirsch
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Patent number: 10103227Abstract: A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.Type: GrantFiled: August 4, 2017Date of Patent: October 16, 2018Assignee: Infineon Technologies Austria AGInventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
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Patent number: 9859272Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).Type: GrantFiled: July 14, 2016Date of Patent: January 2, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
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Publication number: 20170338306Abstract: A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.Type: ApplicationFiled: August 4, 2017Publication date: November 23, 2017Inventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
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Patent number: 9595619Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.Type: GrantFiled: August 10, 2015Date of Patent: March 14, 2017Assignee: Infineon Technologies AGInventors: Holger Hüsken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Rösner, Holger Schulze
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Patent number: 9577080Abstract: A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.Type: GrantFiled: June 8, 2015Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
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Publication number: 20170025408Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).Type: ApplicationFiled: July 14, 2016Publication date: January 26, 2017Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
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Patent number: 9548370Abstract: A transistor device includes an individual transistor cell arranged in a transistor cell field on a semiconductor body, the individual transistor cell having a gate electrode. The transistor device further includes a gate contact, electrically coupled to the gate electrode and configured to switch on the individual transistor cell by providing a gate current in a first direction and configured to switch off the individual transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction. The transistor device also includes a gate-resistor structure monolithically integrated in the transistor device. The gate-resistor structure provides a first resistance for the gate current when the gate current flows in the first direction, and provides a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.Type: GrantFiled: April 21, 2015Date of Patent: January 17, 2017Assignee: Infineon Technologies AGInventors: Stephan Voss, Peter Tuerkes, Holger Huesken
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Patent number: 9515149Abstract: A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The active region includes a drift region formed by at least a part of the substrate layer, a body region of the second conductivity type formed on at least a part of the drift region, a source region of a first conductivity type disposed in the body region, and a first doped region of the first conductivity type at least partially disposed under the body region. A groove extends downward from a top of the substrate layer and contains a shielding electrode. A depth of the groove is greater than that of the first doped region. A gate at least partially formed above at least a part of the source region and the body region is electrically insulated from the shielding electrode.Type: GrantFiled: June 4, 2015Date of Patent: December 6, 2016Assignee: Infineon Technologies AGInventors: Frank Dieter Pfirsch, Holger Huesken, Hans-Joachim Schulze
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Patent number: 9490354Abstract: A semiconductor body of an IGBT includes: a first base region of a second conductivity type; a source region of a first conductivity type different from the second conductivity type and forming a first pn-junction with the first base region; a drift region of the first conductivity type and forming a second pn-junction with the first base region; a collector region of the second conductivity type; at least one trench filled with a gate electrode and having a first trench portion of a first width and a second trench portion of a second width, the second width being different from the first width; and a field stop region having the first conductivity type and located between the drift region and the collector region. The field stop region includes a plurality of buried regions having the second conductivity type.Type: GrantFiled: April 24, 2014Date of Patent: November 8, 2016Assignee: Infineon Technologies AGInventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
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Patent number: 9419080Abstract: A semiconductor device includes a pn junction between a drift zone and a charge-carrier transfer region in a semiconductor body. An access channel provides a permanent charge carrier path connecting the drift zone with a recombination region through a separation region between the drift zone and the recombination region. The access channel adjusts a plasma density in the drift zone and the recombination region.Type: GrantFiled: December 11, 2013Date of Patent: August 16, 2016Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Hans-Joachim Schulze, Peter Irsigler, Holger Huesken, Roman Baburske
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Publication number: 20160043237Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.Type: ApplicationFiled: August 10, 2015Publication date: February 11, 2016Inventors: Holger Hüsken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Rösner, Holger Schulze
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Publication number: 20160035821Abstract: A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The active region includes a drift region formed by at least a part of the substrate layer, a body region of the second conductivity type formed on at least a part of the drift region, a source region of a first conductivity type disposed in the body region, and a first doped region of the first conductivity type at least partially disposed under the body region. A groove extends downward from a top of the substrate layer and contains a shielding electrode. A depth of the groove is greater than that of the first doped region. A gate at least partially formed above at least a part of the source region and the body region is electrically insulated from the shielding electrode.Type: ApplicationFiled: June 4, 2015Publication date: February 4, 2016Inventors: Frank Dieter Pfirsch, Holger Huesken, Hans-Joachim Schulze
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Publication number: 20150357449Abstract: A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.Type: ApplicationFiled: June 8, 2015Publication date: December 10, 2015Inventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
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Patent number: 9123828Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.Type: GrantFiled: November 14, 2013Date of Patent: September 1, 2015Assignee: Infineon Technologies AGInventors: Holger Hüsken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Rösner, Holger Schulze