Patents by Inventor Holm Geisler

Holm Geisler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9021894
    Abstract: Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Patent number: 8950269
    Abstract: Generally, the subject matter disclosed herein relates to testing pillar bumps formed on a semiconductor chip so as to detect the presence of anomalous stiff pillar bumps. One illustrative method disclosed herein includes positioning a test probe adjacent to a side of a pillar bump formed above a metallization system of a semiconductor chip, and performing a lateral force test on the pillar bump by contacting the side of the pillar bump with the test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Patent number: 8829675
    Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140077368
    Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140026676
    Abstract: Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140027902
    Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140026675
    Abstract: Generally, the subject matter disclosed herein relates to testing pillar bumps formed on a semiconductor chip so as to detect the presence of anomalous stiff pillar bumps. One illustrative method disclosed herein includes positioning a test probe adjacent to a side of a pillar bump formed above a metallization system of a semiconductor chip, and performing a lateral force test on the pillar bump by contacting the side of the pillar bump with the test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Patent number: 8623754
    Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 7, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Patent number: 8479578
    Abstract: The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Holm Geisler, Matthias Lehr, Frank Kuechenmeister, Michael Grillberger
  • Publication number: 20130087907
    Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bump structure above a first metallization layer of a metallization system of the semiconductor chip, and a metal feature in the first metallization layer, wherein at least a first portion of the metal feature is located closer to a center of the semiconductor chip than any portion of the bump structure, and at least a second portion of the metal feature is positioned below the bump structure.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Matthias U. Lehr, Holm Geisler, Frank Kuechenmeister
  • Publication number: 20110209548
    Abstract: The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.
    Type: Application
    Filed: November 4, 2010
    Publication date: September 1, 2011
    Inventors: Holm Geisler, Matthias Lehr, Frank Kuechenmeister, Michael Grillberger
  • Patent number: 7441446
    Abstract: By digitizing the UFM signal without using a lock-in amplifier, substantially all of the information initially contained in the UFM output signal may be maintained and may then be used for further data processing. Consequently, any type of model or evaluation algorithm may be used without being restricted to a very narrow bandwidth, as is the case in lock-in based techniques. The digitizing is performed on a real-time basis, wherein a complete UFM curve is digitized and stored for each scan position. In this way, quantitative meaningful values for specific surface-related characteristics with a nanometer resolution may be obtained.
    Type: Grant
    Filed: May 25, 2008
    Date of Patent: October 28, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dmytro Chumakov, Holm Geisler, Ehrenfried Zschech
  • Publication number: 20070044544
    Abstract: By digitizing the UFM signal without using a lock-in amplifier, substantially all of the information initially contained in the UFM output signal may be maintained and may then be used for further data processing. Consequently, any type of model or evaluation algorithm may be used without being restricted to a very narrow bandwidth, as is the case in lock-in based techniques. The digitizing is performed on a real-time basis, wherein a complete UFM curve is digitized and stored for each scan position. In this way, quantitative meaningful values for specific surface-related characteristics with a nanometer resolution may be obtained.
    Type: Application
    Filed: May 25, 2006
    Publication date: March 1, 2007
    Inventors: Dmytro Chumakov, Holm Geisler, Ehrenfried Zschech