Patents by Inventor Hon-Yeh Lee

Hon-Yeh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Motherboard module having switchable PCI-E lane
    Patent number: 10083145
    Abstract: A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th processor pin sets of the CPU are switchably electrically connected to 1st to a-th first PCI-E pin sets of the first PCI-E slot or (2N?a+1)th to 2N-th second PCI-E pin sets of the second PCI-E slot via the first switch to form PCI-E lanes whose number is a. (a+1)-th to 2N-th processor pin sets of the CPU are connected to the second input terminal of the second switch, and the second output terminal of the second switch is switchably electrically connected to (a+1)-th to 2N-th first PCI-E pin sets of the first PCI-E slot or 1st to (2N?a)th second PCI-E pin sets of the second PCI-E slot to form PCI-E lanes whose number is 2N?a, wherein 1<a<2N.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 25, 2018
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Pei-Hua Sun, Hon-Yeh Lee, Yen-Yun Chang
  • MOTHERBOARD MODULE HAVING SWITCHABLE PCI-E LANE
    Publication number: 20180011814
    Abstract: A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th processor pin sets of the CPU are switchably electrically connected to 1st to a-th first PCI-E pin sets of the first PCI-E slot or (2N?a+1)th to 2N-th second PCI-E pin sets of the second PCI-E slot via the first switch to form PCI-E lanes whose number is a. (a+1)-th to 2N-th processor pin sets of the CPU are connected to the second input terminal of the second switch, and the second output terminal of the second switch is switchably electrically connected to (a+1)-th to 2N-th first PCI-E pin sets of the first PCI-E slot or 1st to (2N?a)th second PCI-E pin sets of the second PCI-E slot to form PCI-E lanes whose number is 2N?a, wherein 1<a<2N.
    Type: Application
    Filed: September 2, 2016
    Publication date: January 11, 2018
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Pei-Hua Sun, Hon-Yeh Lee, Yen-Yun Chang