Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: The present disclosure relates to an electronic device and its execution method and a computer-readable medium. An electronic device, comprising: a memory having instructions stored thereon; a processor configured to execute instructions stored on the memory to cause the electronic device to perform the following operations: analyzing an original video stream being played to determine start time and duration of a first video stream part to be replaced in the original video stream; retrieving a second video stream part with the same duration; playing the second video stream part in a front end at the determined start time to play the original video stream in a backend; and playing the original video stream in the front end after finishing playing the second video stream part.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.

Abstract: The present disclosure relates to an electronic device and its execution method and a computer-readable medium. An electronic device, comprising: a memory having instructions stored thereon; a processor configured to execute instructions stored on the memory to cause the electronic device to perform the following operations: analyzing an original video stream being played to determine start time and duration of a first video stream part to be replaced in the original video stream; retrieving a second video stream part with the same duration; playing the second video stream part in a front end at the determined start time to play the original video stream in a backend; and playing the original video stream in the front end after finishing playing the second video stream part.

Abstract: A commutation error compensation method for an electric motor includes: when a rotor, that has not been corrected, in an electric motor rotates in a set direction, collecting a position signal and a three-phase current signal of the rotor, wherein the position signal of the rotor represents the rotation angle of the rotor; filtering processing on the three-phase current signal to obtain a fundamental component of the three-phase current signal, and determining a position error compensation signal of the electric motor on the basis of the fundamental component of the three-phase current signal; determining an ideal phase interval of the rotor according to the position error compensation signal and the position signal of the rotor; and determining an adjustment method for the rotor of the electric motor according to the ideal phase interval of the rotor, and commutating the rotor of the electric motor according to the adjustment method.

Abstract: A commutation control method, a device for a brushless direct current motor, and a storage medium are described. The method includes performing detection on a position of a rotor in a brushless direct current motor. The detection is further configured to be triggered by commutation of the brushless direct current motor. The method includes determining, for the brushless direct current motor, a first drive scheme corresponding to the detected position of the rotor, the first drive scheme indicates a manner in which a three-phase full-bridge circuit of the brushless direct current motor operates; updating a pulse width modulation (PWM) drive signal, the updating is performed on the basis of the first drive scheme; and using the updated PWM drive signal to control the brushless direct current motor to perform commutation.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: The disclosure provides an electronic device, including a display panel, an infrared light source, and an infrared cutoff layer. The display panel includes a display surface, a back surface opposite to the display surface, and a side surface connecting the display surface and the back surface. The infrared light source is disposed adjacent to the side surface of the display panel and is configured to emit infrared light. The display panel includes an overlapping region in which the infrared light source overlaps with the side surface as viewed from a side view. The infrared cutoff layer is attached to the side surface and the back surface of the display panel, and covers at least the overlapping region and an extension region in which the overlapping region extends respectively in a transverse direction and toward the back surface by a preset distance.

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Abstract: A commutation error compensation method for an electric motor includes: when a rotor, that has not been corrected, in an electric motor rotates in a set direction, collecting a position signal and a three-phase current signal of the rotor, wherein the position signal of the rotor represents the rotation angle of the rotor; filtering processing on the three-phase current signal to obtain a fundamental component of the three-phase current signal, and determining a position error compensation signal of the electric motor on the basis of the fundamental component of the three-phase current signal; determining an ideal phase interval of the rotor according to the position error compensation signal and the position signal of the rotor; and determining an adjustment method for the rotor of the electric motor according to the ideal phase interval of the rotor, and commutating the rotor of the electric motor according to the adjustment method.

Abstract: A stator includes a stator core having a plurality of inner stator teeth and a ring-shaped stator yoke. The plurality of inner stator teeth is arranged on an inner side of the stator yoke at intervals along a circumferential direction of the stator yoke, and extends to a central axis of the stator yoke, so that stator slots are formed between adjacent inner stator teeth; and a first phase winding, a second phase winding, and a third phase winding wound around two adjacent inner stator teeth. Each of the stator slots is divided into an inner space and an outer space along a radial direction of the stator yoke; each of the first phase winding, the second phase winding, and the third phase winding penetrates through inner spaces or outer spaces of the corresponding two stator slots.

Abstract: A commutation control method, a device for a brushless direct current motor, and a storage medium are described. The method includes performing detection on a position of a rotor in a brushless direct current motor. The detection is further configured to be triggered by commutation of the brushless direct current motor. The method includes determining, for the brushless direct current motor, a first drive scheme corresponding to the detected position of the rotor, the first drive scheme indicates a manner in which a three-phase full-bridge circuit of the brushless direct current motor operates; updating a pulse width modulation (PWM) drive signal, the updating is performed on the basis of the first drive scheme; and using the updated PWM drive signal to control the brushless direct current motor to perform commutation.

Abstract: A coding disc having a first surface and a second surface opposite to the first surface is provided. The coding disc includes a first aperture and a second aperture. The first aperture penetrates the coding disc from the first surface of the coding disc to the second surface of the coding disc. The first aperture has a first width. The second aperture penetrates the coding disc from the first surface of the coding disc to the second surface of the coding disc. The second aperture has a second width. The second width of the second aperture is different from the first width of the first aperture.

Abstract: The present disclosure relates to a power factor correction circuit, a control method, and an electrical appliance. The power factor correction circuit may include: a power regulation branch, including a first switching unit, a second switching unit and a branch sampling resistor connected in series sequentially; an inductive branch, connected between an AC power source and a power regulation branch; a rectifier branch, including a first rectifier unit and a second rectifier unit, the rectifier branch may include a main line sampling resistor; a capacitance branch; a control circuit sampling a branch current flowing through each of the branch sampling resistors and a main line current flowing through the main line sampling resistor respectively, and controlling the switching of each power regulation branch sequentially. With the branch sampling resistor and the main line sampling resistor, the overall cost of the power factor correction circuit may be reduced.

Abstract: Video decoding and encoding methods and apparatuses are provided. The decoding method includes: obtaining a first parameter set corresponding to a to-be-decoded video frame; determining an effective quantization matrix (QM) according to syntax elements included in the first parameter set, the effective QM being a QM actually used for inversely quantizing quantized transform coefficients during decoding of the to-be-decoded video frame; and decoding the effective QM.

Abstract: A method, system, and computer program product for interactive commenting in an on-demand video includes a processor to receive an on-demand video file selection from a first user for display on a first user device. The processor can receive a first input from the first user via a first graphical user interface at a first time of the video file and determine a time interval of the selected video file associated with the first input. The processor can identify one or more second users on one or more second user devices within the time interval of the video file and display the first input from the first user to the one or more second users within the time interval of the video file on the one or more second user devices via one or more second graphical user interfaces over the video file.