Patents by Inventor Hong-bum Park
Hong-bum Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120475Abstract: The present disclosure relates to a cathode active material for an all-solid-state battery with a controlled particle size and a method for preparing the same. In particular, the cathode active material includes lithium and a transition metal, wherein the cathode active material has a single peak in the range of 1 ?m to 10 ?m as a result of particle size distribution (PSD) analysis.Type: ApplicationFiled: May 4, 2023Publication date: April 11, 2024Inventors: Sung Woo NOH, Hong Seok MIN, Sang Heon LEE, Jeong Hyun SEO, Im Sul SEO, Chung Bum LIM, Ju Yeong SEONG, Je Sik PARK
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Patent number: 11380651Abstract: A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.Type: GrantFiled: May 5, 2020Date of Patent: July 5, 2022Assignee: SK hynix Inc.Inventors: Hong-Bum Park, Jeong-Hyun Park, Suk-Won Lee
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Publication number: 20210111152Abstract: A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.Type: ApplicationFiled: May 5, 2020Publication date: April 15, 2021Applicant: SK hynix Inc.Inventors: Hong-Bum PARK, Jeong-Hyun PARK, Suk-Won LEE
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Patent number: 10056491Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.Type: GrantFiled: January 31, 2017Date of Patent: August 21, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seong Hoon Jeong, Hong Bum Park, HanMei Choi, Jae Young Park, Seung Hyun Lim
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Publication number: 20170358680Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.Type: ApplicationFiled: January 31, 2017Publication date: December 14, 2017Inventors: Seong Hoon JEONG, Hong Bum PARK, HanMei CHOI, Jae Young PARK, Seung Hyun LIM
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Publication number: 20170330905Abstract: A pixel array may include an array of microlenses, an array of photodetectors, and an array of color filters. The array of microlenses concentrate incoming light through respective filters in the array of color filters to respective photodetectors in the array of photodetectors. An anti-reflective layer is included between the photodetectors and color filters. The anti-reflective layer includes a first layer having a first index of refraction, a second layer closer to the color filter than the first layer having a second, higher, index of refraction, and a lattice adjusting layer between the first and second layers. The second layer includes a rutile phase TiO2 layer and the lattice adjusting layer includes a crystalline material having a lattice constant similar to that of the rutile phase TiO2 layer.Type: ApplicationFiled: January 3, 2017Publication date: November 16, 2017Inventors: Yong Suk Tak, Hong Bum Park, Won Oh Seo, Guk Hyon Yon, Ju Ri Lee
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Patent number: 9502532Abstract: Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.Type: GrantFiled: May 8, 2015Date of Patent: November 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hong Bum Park, Dong Chan Suh, Kwan Heum Lee
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Publication number: 20160086943Abstract: A semiconductor device includes a substrate, an isolation layer on the substrate, and at least one active fin on the substrate. The isolation layer includes a first surface opposite a second surface. The first surface is contiguous with the substrate. The at least one active fin protrudes from the substrate and includes a first region having a side wall above the second surface of the isolation layer and a second region on the first region. The second region has an upper surface. The first region has a first width contiguous with the second surface of the isolation layer and a second width contiguous with the second region. The second width is 60% or greater than the first width (e.g., 60% to 100%).Type: ApplicationFiled: September 17, 2015Publication date: March 24, 2016Inventors: Sun Young LEE, Jae Young Park, Han Ki Lee, Bon Young Koo, Hong Bum Park, Young Su Chung, Jae Jong Han
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Publication number: 20160020301Abstract: Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.Type: ApplicationFiled: May 8, 2015Publication date: January 21, 2016Inventors: Hong Bum Park, Dong Chan Suh, Kwan Heum Lee
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Publication number: 20140287564Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.Type: ApplicationFiled: May 27, 2014Publication date: September 25, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Keum-Seok Park, Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang, Hong-Bum Park
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Patent number: 8298865Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.Type: GrantFiled: January 25, 2012Date of Patent: October 30, 2012Assignee: Hynix Semiconductor Inc.Inventors: Young Berm Jung, Hong Bum Park, Young Geon Kwon, Seong Kwon Chin, Byeung Ho Kim, Seok Koo Jung
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Publication number: 20120118495Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Young Berm JUNG, Hong Bum PARK, Young Geon KWON, Seong Kwon CHIN, Byeung Ho KIM, Seok Koo JUNG
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Publication number: 20120091469Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.Type: ApplicationFiled: October 12, 2011Publication date: April 19, 2012Inventors: Keum-Seok Park, Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang, Hong-Bum Park
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Patent number: 8125086Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.Type: GrantFiled: May 26, 2009Date of Patent: February 28, 2012Assignee: Hynix Semiconductor Inc.Inventors: Young Berm Jung, Hong Bum Park, Young Geon Kwon, Seong Kwon Chin, Byeung Ho Kim, Seok Koo Jung
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Publication number: 20110275197Abstract: A method of forming a semiconductor memory device, a semiconductor memory device, and a memory system, the method including forming a thin film structure on a semiconductor substrate such that the thin film structure includes a plurality of thin films; patterning the thin film structure to form a through region in the thin film structure; forming a first silicon film using a first precursor such that the first silicon film covers the through region; and forming a second silicon film on the first silicon film using a second precursor, wherein the first precursor is different from the second precursor.Type: ApplicationFiled: May 4, 2011Publication date: November 10, 2011Inventors: Hong-bum PARK, Dae-Han Yoo, Eun-Young Lee, Yongwoo Hyung, Youngsub You, Jinkwon Bok
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Publication number: 20090294972Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.Type: ApplicationFiled: May 26, 2009Publication date: December 3, 2009Inventors: Young Berm JUNG, Hong Bum PARK, Young Geon KWON, Seong Kwon CHIN, Byeung Ho KIM, Seok Koo JUNG
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Patent number: 7482242Abstract: Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities.Type: GrantFiled: September 20, 2006Date of Patent: January 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Bum Park, Woo-Sung Lee, Nam-Kyu Kim, Jung-Hee Chung, Jae-Hyoung Choi
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Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors
Patent number: 7422943Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.Type: GrantFiled: March 22, 2006Date of Patent: September 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-cheol Lee, Young-sun Kim, Jung-hee Chung, Jae-hyoung Choi, Se-hoon Oh, Hong-bum Park -
Publication number: 20080054400Abstract: Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may be on the lower electrode. The dielectric layer may have a uniform thickness. The upper electrode may be on the dielectric layer. The upper electrode may have a more uniform thickness. The capping layer may be on the upper electrode. The capping layer may include a silicon germanium layer doped with p-type impurities. The barrier layer may be between the upper electrode and the capping layer to prevent (or reduce) the p-type impurities from infiltrating into the dielectric layer.Type: ApplicationFiled: July 26, 2007Publication date: March 6, 2008Inventors: Woo-Sung Lee, Hong-Bum Park, Hyun-Jin Shin, Jong-Bom Seo
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Publication number: 20070066015Abstract: Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities.Type: ApplicationFiled: September 20, 2006Publication date: March 22, 2007Inventors: Hong-Bum Park, Woo-Sung Lee, Nam-Kyu Kim, Jung-Hee Chung, Jae-Hyoung Choi