Patents by Inventor Hong-Chen Cheng
Hong-Chen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240174749Abstract: This disclosure provides a method for treating a subject afflicted with a tumor or a cancer, wherein the method comprises administering to the subject therapeutically effective amounts of an anti-TIM3 antibody, alone or in combination with an inhibitor of the PD-1 signaling pathway (e.g., anti-PD-1 antibody). In some embodiments, the antibody is administered as a flat dose or a weight-based dose.Type: ApplicationFiled: September 27, 2023Publication date: May 30, 2024Applicant: Bristol-Myers Squibb CompanyInventors: Xiao Min SCHEBYE, Mark J. SELBY, Michelle Minhua HAN, Christine BEE, Andy X. DENG, Anan CHUNTHARAPAI, Brigitte DEVAUX, Huiming LI, Paul O. SHEPPARD, Alan J. KORMAN, Daniel F. ARDOUREL, Ekaterina DEYANOVA, Richard Yu-Cheng HUANG, Guodong CHEN, Michelle Renne KUHNE, Hong-An TRUONG, Poliana PATAH, Jeffrey R. JACKSON, Ronald A. FLEMING
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Publication number: 20240096757Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
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Patent number: 11919962Abstract: Provided herein are antibodies that bind to the alpha subunit of an IL-7 receptor (IL-7R?). Also provided are uses of these antibodies in therapeutic applications, such as treatment of inflammatory diseases. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain regions of the antibodies, and vectors comprising the polynucleotides.Type: GrantFiled: April 16, 2021Date of Patent: March 5, 2024Assignee: Bristol Myers-Squibb CompanyInventors: Aaron Paul Yamniuk, Scott Ronald Brodeur, Ekaterina Deyanova, Richard Yu-Cheng Huang, Yun Wang, Alfred Robert Langish, Guodong Chen, Stephen Michael Carl, Hong Shen, Achal Mukundrao Pashine, Lin Hui Su
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Patent number: 11854943Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.Type: GrantFiled: January 12, 2023Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yun-Han Lee, Lee-Chung Lu
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Patent number: 11723195Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.Type: GrantFiled: May 20, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Hung-Jen Liao, Cheng Hung Lee
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Publication number: 20230170281Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.Type: ApplicationFiled: January 12, 2023Publication date: June 1, 2023Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
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Patent number: 11562946Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.Type: GrantFiled: March 23, 2021Date of Patent: January 24, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yun-Han Lee, Lee-Chung Lu
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Publication number: 20220293492Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.Type: ApplicationFiled: March 23, 2021Publication date: September 15, 2022Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
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Patent number: 11138359Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: August 31, 2020Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20210272968Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Tsung-Hsien HUANG, Hong-Chen CHENG, Hung-Jen LIAO, Cheng Hung LEE
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Patent number: 11024634Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.Type: GrantFiled: November 30, 2018Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee, Hung-Jen Liao
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Publication number: 20200394355Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10866281Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.Type: GrantFiled: April 19, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
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Patent number: 10762269Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20190325104Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Publication number: 20190242943Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.Type: ApplicationFiled: April 19, 2019Publication date: August 8, 2019Inventors: WEI-PIN CHANGCHIEN, HONG-CHEN CHENG, PEI-YING LIN, HSIN-WU HSU
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Patent number: 10339248Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: GrantFiled: December 20, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 10267853Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.Type: GrantFiled: April 25, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
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Publication number: 20190096895Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Inventors: Tsung-Hsien HUANG, Hong-Chen CHENG, Cheng Hung LEE, Hung-Jen LIAO
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Patent number: 10170487Abstract: A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.Type: GrantFiled: October 25, 2016Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee, Hung-Jen Liao