Patents by Inventor Hong Gu Ji
Hong Gu Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955961Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.Type: GrantFiled: August 2, 2022Date of Patent: April 9, 2024Assignee: Electronics and Telecommunications Research InstituteInventors: Hong Gu Ji, Dong Min Kang, Byoung-Gue Min, Jongmin Lee, Kyu Jun Cho
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Patent number: 11817826Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.Type: GrantFiled: August 11, 2022Date of Patent: November 14, 2023Assignee: Electronics and Telecommunications Research InstituteInventors: Woojin Chang, Dong Min Kang, Byoung-Gue Min, Jong Yul Park, Jongmin Lee, Yoo Jin Jang, Kyu Jun Cho, Hong Gu Ji
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Publication number: 20230142553Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.Type: ApplicationFiled: August 11, 2022Publication date: May 11, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: Woojin CHANG, Dong Min KANG, BYOUNG-GUE MIN, JONG YUL PARK, JONGMIN LEE, YOO JIN JANG, KYU JUN CHO, Hong Gu JI
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Publication number: 20230115787Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.Type: ApplicationFiled: August 2, 2022Publication date: April 13, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: Hong Gu JI, Dong Min KANG, BYOUNG-GUE MIN, JONGMIN LEE, Kyu Jun CHO
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Patent number: 10608102Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.Type: GrantFiled: September 20, 2018Date of Patent: March 31, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Min Jeong Shin, Jeong Jin Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Hyung Seok Lee, Jong-Won Lim, Sungjae Chang, Hyunwook Jung, Kyu Jun Cho, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Sang-Heung Lee, Jongmin Lee, Hong Gu Ji
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Patent number: 10256811Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.Type: GrantFiled: July 20, 2017Date of Patent: April 9, 2019Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woojin Chang, Jong-Won Lim, Dong Min Kang, Dong-Young Kim, Seong-il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Min Jeong Shin, Hokyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jongmin Lee, Sungjae Chang, Yoo Jin Jang, Hyunwook Jung, Kyu Jun Cho, Hong Gu Ji
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Publication number: 20190103483Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.Type: ApplicationFiled: September 20, 2018Publication date: April 4, 2019Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun AHN, Min Jeong SHIN, Jeong Jin KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Hyung Seok LEE, Jong-Won LIM, Sungjae CHANG, Hyunwook JUNG, Kyu Jun CHO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Sang-Heung LEE, Jongmin LEE, Hong Gu JI
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Publication number: 20190081166Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.Type: ApplicationFiled: July 6, 2018Publication date: March 14, 2019Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae Won DO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Hae Cheon KIM, Byoung-Gue MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jongmin LEE, Jong-Won LIM, Sungjae CHANG, Yoo Jin JANG, Hyunwook JUNG, Kyu Jun CHO, Hong Gu JI
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Publication number: 20180145684Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.Type: ApplicationFiled: July 20, 2017Publication date: May 24, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Woojin CHANG, Jong-Won LIM, Dong Min KANG, Dong-Young KIM, Seong-il KIM, Hae Cheon KIM, Jae Won DO, BYOUNG-GUE MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, JONGMIN LEE, Sungjae CHANG, Yoo Jin JANG, HYUNWOOK JUNG, Kyu Jun CHO, Hong Gu JI
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Publication number: 20160233834Abstract: A power amplifier for compensating for a phase delay characteristic and a power synthesizing apparatus using the power amplifier are provided. A microwave frequency amplifying apparatus may include an amplifier configured to amplify a first power and to generate a second power, and a phase shifter configured to compensate for a phase of at least one of the first power and the second power and connected in series to the amplifier.Type: ApplicationFiled: February 11, 2016Publication date: August 11, 2016Inventor: Hong Gu JI
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Publication number: 20150137907Abstract: Provided is a directional coupler having high isolation, the directional coupler including a first directional coupler including a first main line and a first sub-line, and a second directional coupler including a second main line and a second sub-line, wherein the first directional coupler is connected to the second directional coupler in series.Type: ApplicationFiled: November 7, 2014Publication date: May 21, 2015Inventors: Hong Gu JI, In Kwon JU, In Bok YOM
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Publication number: 20150137877Abstract: Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.Type: ApplicationFiled: June 19, 2014Publication date: May 21, 2015Inventors: Yun Ho CHOI, Youn Sub NOH, Hong Gu JI, Jin Cheol JEONG, In Bok YOM
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Publication number: 20140184438Abstract: A transmit/receive module for radar may include a radio frequency (RF) circuit unit including an RF substrate and an RF part; and a direct current (DC) power supply circuit unit including a printed circuit board (PCB) and a DC power supply circuit part. The RF circuit unit and the DC power supply circuit unit may be disposed so that a rear surface of the RF circuit unit faces a rear surface of the DC power supply circuit unit, and may be assembled to have a separate space using at least one separation wall.Type: ApplicationFiled: December 23, 2013Publication date: July 3, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Pil Chang, In Bok Yom, Youn Sub Noh, Jin Cheol Jeong, Hong Gu Ji, Man Seok Uhm
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Patent number: 8697507Abstract: Provided are a transistor of a semiconductor device and a method of fabricating the same.Type: GrantFiled: January 11, 2011Date of Patent: April 15, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Kyoung Mun, Hong Gu Ji, Ho Kyun Ahn, Hae Cheon Kim
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Publication number: 20130293295Abstract: Provided is a compact RF power amplifier including: a Doherty amplifier comprising a carrier amplifier comprising a first input impedance matching unit, a first amplifier, and a first output impedance matching unit, and a peaking amplifier comprising a second input impedance matching unit, a second amplifier, and a second output impedance matching unit, in which when a power level of the first RF amplified signal reaches a predetermined power level, the peaking amplifier outputs the second RF amplified signal.Type: ApplicationFiled: March 15, 2013Publication date: November 7, 2013Applicant: Electronics and Telecommunications Research InstituteInventors: Youn Sub NOH, In Bok YOM, Dong Pil CHANG, Hong Gu JI
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Patent number: 8294521Abstract: Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.Type: GrantFiled: August 12, 2010Date of Patent: October 23, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Dong Min Kang, Hong Gu Ji, Hokyun Ahn, Jong-Won Lim, Woojin Chang, Sang-Heung Lee, Dong-Young Kim, Hae Cheon Kim
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Patent number: 8058658Abstract: Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.Type: GrantFiled: April 9, 2009Date of Patent: November 15, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Heung Lee, Hae Cheon Kim, Dong Min Kang, Dong-Young Kim, Jae Kyoung Mun, Hokyun Ahn, Jong-Won Lim, Woo Jin Chang, Hong Gu Ji, Eun Soo Nam
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Patent number: 7973368Abstract: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.Type: GrantFiled: May 19, 2008Date of Patent: July 5, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Jong Won Lim, Ho Kyun Ahn, Hong Gu Ji, Woo Jin Chang, Jae Kyoung Mun, Hae Cheon Kim, Hyun Kyu Yu
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Publication number: 20110143507Abstract: Provided are a transistor of a semiconductor device and a method of fabricating the same.Type: ApplicationFiled: January 11, 2011Publication date: June 16, 2011Inventors: Jae Kyoung Mun, Hong Gu Ji, Ho Kyun Ahn, Hae Cheon Kim
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Patent number: 7933576Abstract: A sub-harmonic mixer is provided, which includes: a mixer core having first and second transistors performing switching operations in response to a local oscillator (LO) signal and a radio frequency (RF) signal; a power source applying bias maximizing nonlinearity of a transistor included in the mixer core; an RF port applying an RF signal to the mixer core; an LO port applying an LO signal to the mixer core; and first and second phase delay circuits in which the RF signals applied to the first and second transistors have a 180-degree phase difference.Type: GrantFiled: November 28, 2007Date of Patent: April 26, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Hong Gu Ji, Hae Cheon Kim, Hyun Kyu Yu