Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: An apparatus comprising a test termination card having a first set of connections and a second set of connections. The first set of connections may be configured to connect to a specific pinout of a device under test. The second set of connections may be configured to connect to a general pinout of a tester load board. The termination card may toggle between (a) connecting the first set of connectors to the second set of connectors to implement a first test type and (b) disconnecting the first set of connectors from the second set of connectors to implement a second test type.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

Abstract: Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

Abstract: A method and apparatus for decoupling a voltage supply from a semiconductor device is provided. A substrate has a plurality of spaced apart electrical connections positioned on thereon, wherein at least first and second ones of the connections are coupled to first and second terminals of a voltage supply respectively. A capacitor is coupled to the substrate and interstitially positioned within the spaced apart connections. The capacitor has first and second leads coupled with the first and second terminals of the voltage supply. A semiconductor device is coupled to the substrate in mating relationship with the pattern of spaced apart electrical connections, wherein the capacitor is positioned below the semiconductor device and immediately adjacent the voltage supply terminals of the semiconductor device.