Abstract: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film.

Abstract: A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the secon

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract: A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

Abstract: Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate.

Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

Abstract: A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

Abstract: A gate driving unit for a liquid crystal display device including a plurality of liquid crystal pixels, first to Nth gate lines, a plurality of liquid crystal capacitors and a plurality of thin film transistors, includes first and second clock signal lines for providing first and second clock signals; first to Nth shift registers respectively corresponding to the first to Nth gate lines, the first to Nth shift registers receiving one of the first clock signal and the second clock signal and outputting first to Nth scanning signals, respectively; a redundant repair shift register as (N+1)th shift register receiving one of first and second clock signals and outputting a repair scanning signal; a plurality of first switches for respectively connecting one of the first and second clock signal lines to the first to Nth shift registers and the redundant repair shift register; a plurality of second switches for respectively switching a connection of the first to Nth shift registers with the first to Nth gate lines;

Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

Abstract: Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

Abstract: Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

Abstract: Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract: A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract: Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate.

Abstract: Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer.

Abstract: A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed to have a lower capping layer pattern and an upper capping layer pattern. The lower capping layer pattern is formed to a smaller width than the upper capping layer pattern.

Abstract: Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from the via holes without damaging or removing the interlayer dielectric layer.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.