Abstract: Methods and apparatus for decoding received uplink transmissions using log-likelihood ratio optimization. In an embodiment, a method includes soft-demapping resource elements based on soft-demapping parameters as part of a process to generate log-likelihood ratios (LLR) values, decoding the LLRs to generate decoded data, and identifying a target performance value. The method also includes determining a performance metric from the decoded data, and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value.

Abstract: Methods and apparatus for providing a resource element identification system to process received uplink transmissions. In an embodiment, a method is provided that includes receiving soft-demapped symbols that comprises resource elements. The method also includes descrambling the resource elements of the symbols one-by-one using descrambling bits generated by at least one linear feedback shift register (LFSR). After each symbol is descrambled, a state of the at least one LFSR is stored as a stored state. The method also comprises restoring the stored state to the at least one LFSR before a next symbol is descrambled so that generation of the descrambling bits continues from symbol to symbol. The method also comprises forwarding the descrambled symbols to a downstream combining function.

Abstract: Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.

Abstract: Methods and apparatus for providing a demapping system with phase compensation to demap uplink transmissions. In an embodiment, a method is provided that includes detecting a processing type associated with a received uplink transmission, and when the detected processing type is a first processing type then performing the following operations: removing resource elements containing reference signals from the uplink transmission; layer demapping remaining resource elements of the uplink transmission into two or more layers; phase compensating all layers to generate phase compensated layers; and soft-demapping all phase compensated layers to produce phase compensated soft-demapped bits.

Abstract: Methods and apparatus for providing a demapping system to demap uplink transmissions. In an embodiment, a method is provided that includes detecting a processing type associated with a received uplink transmission, and when the detected processing type is a first processing type then performing the following operations: removing resource elements containing reference signals from the uplink transmission; layer demapping remaining resource elements of the uplink transmission into two or more layers; soft-demapping the two or more layers to produce soft-demapped data. The method also includes descrambling the soft-demapped data to produce descrambled data, and processing the descrambled data to generate uplink control information (UCI).

Abstract: Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.

Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.

Abstract: Methods and apparatus for providing a resource element identification system to process received uplink transmissions. In an embodiment, a method is provided that includes receiving soft-demapped symbols that comprises resource elements. The method also includes descrambling the resource elements of the symbols one-by-one using descrambling bits generated by at least one linear feedback shift register (LFSR). After each symbol is descrambled, a state of the at least one LFSR is stored as a stored state. The method also comprises restoring the stored state to the at least one LFSR before a next symbol is descrambled so that generation of the descrambling bits continues from symbol to symbol. The method also comprises forwarding the descrambled symbols to a downstream combining function.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.

Abstract: Methods and apparatus for providing a demapping system to demap uplink transmissions. In an embodiment, a method is provided that includes detecting a processing type associated with a received uplink transmission, and when the detected processing type is a first processing type then performing the following operations: removing resource elements containing reference signals from the uplink transmission; layer demapping remaining resource elements of the uplink transmission into two or more layers; soft-demapping the two or more layers to produce soft-demapped data. The method also includes descrambling the soft-demapped data to produce descrambled data, and processing the descrambled data to generate uplink control information (UCI).

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for compressing data streams. In an embodiment, a method includes calculating a probability distribution function (PDF) for scaler data, matching the PDF to PDF templates to determine a closest matching PDF template, and selecting an encoder corresponding to the closest matching PDF template wherein a corresponding encoder identifier is determined. The method also includes encoding the scaler data with the encoder to generate an encoded stream, and transmitting the encoded stream and the encoder identifier.

Abstract: Methods and apparatus for compressing data streams. In an embodiment, a method includes calculating a decomposition of matrix data to generate eigenvectors and associated eigenvalues, determining clusters of the eigenvectors based on weighting the eigenvalues, calculating an eigenvector centroid for each cluster so that a dictionary of centroids is generated, and tagging the eigenvectors with tags, respectively, that identify an associated eigenvector centroid for each eigenvector.

Abstract: Methods and apparatus for two-stage ACK/DTX detection. In an embodiment, a method includes determining a first stage DTX value from bit-domain correlation values, and determining a second stage DTX value from symbol domain correlation values generated from candidate ACK bits. The method also includes determining a DTX decision based on the first stage DTX value and the second stage DTX value.

Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

Abstract: A method utilizing a system encompassing a free pool buffer; a deadlock avoidance buffer; and a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer to reorder out-of-order responses to fetch requests into correct order by: receiving a fetch request on behalf of a consumer; allocating space first in the free pool buffer and when such space is not available then allocating space in a division associated with the consumer in the deadlock avoidance buffer. Issuing segment(s) of the fetch request including associated tag(s) to one of one or more memories; writing response data for each of the segment(s) to the allocated space in the free buffer or the deadlock avoidance buffer according to each of the associated tag(s); and transferring the response data to the consumer according to an entry in an ordering first-in, first-out buffer and an entry in a pending request array.