Patents by Inventor Hong-Nien Lin
Hong-Nien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343781Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: June 27, 2023Publication date: October 26, 2023Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling_Yen YEH, Wilman TSAI, Yee-Chia YEO
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Patent number: 11728332Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: GrantFiled: June 21, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
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Publication number: 20210343705Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: June 21, 2021Publication date: November 4, 2021Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
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Patent number: 11043489Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: GrantFiled: July 30, 2018Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
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Patent number: 10964815Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.Type: GrantFiled: June 12, 2018Date of Patent: March 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hong-Nien Lin, Ming-Heng Tsai, Yong-Yan Lu, Chun-Sheng Liang, Jeng-Ya Yeh
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Patent number: 10937783Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: GrantFiled: March 31, 2017Date of Patent: March 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
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Publication number: 20190378927Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: HONG-NIEN LIN, MING-HENG TSAI, YONG-YAN LU, CHUN-SHENG LIANG, JENG-YA YEH
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Publication number: 20180350800Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
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Publication number: 20180151745Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: March 31, 2017Publication date: May 31, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
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Patent number: 9653552Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: July 8, 2016Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20160322463Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9406800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: December 15, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20160104800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9214554Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: January 28, 2015Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20150206970Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: January 28, 2015Publication date: July 23, 2015Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang-Yu
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Patent number: 8946811Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: July 10, 2006Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 7928474Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.Type: GrantFiled: August 15, 2007Date of Patent: April 19, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.,Inventors: Hong-Nien Lin, Chih-Hsin Ko, Wen-Chin Lee
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Publication number: 20090140351Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 ?.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Hong-Nien Lin, Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee
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Publication number: 20090045411Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.Type: ApplicationFiled: August 15, 2007Publication date: February 19, 2009Inventors: Hong-Nien Lin, Chih-Hsin Ko, Wen-Chin Lee
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Publication number: 20080006908Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang