Abstract: A de-interleaving system includes a generator for generating a write address for storing input audio data of a D2 MAC signal in units of packets, a generator for generating a read address for de-interleaving the stored audio data of the D2 MAC signal in units of packets so that the audio data is arranged in the sequence of pre-interleaving, a plurality of RAMs for storing the audio data of the D2 MAC signal according to the write address applied from the write address generator and for reading the stored audio data according to the read address applied from the read address generator, and several selectors for receiving the write address and read address from the write address generator and read address generator so as to apply the addresses to corresponding RAMs in units of packets of audio data. The system can enhance the error correction capability by receiving D2 MAC signals interleaved in units of packets and de-interleaving audio data in a normal sequence.