Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.

Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.

Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.

Abstract: A method for importing a design in hardware description language (HDL) into a system level design tool includes setting a sampling time. The simulation model template is generated with the sampling time according to a selected simulation model type.

Abstract: A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Abstract: A method for importing a design in hardware description language (HDL) into a system level design tool includes setting a sampling time. The simulation model template is generated with the sampling time according to a selected simulation model type.

Abstract: A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.

Abstract: A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.