Patents by Inventor HONG-SHYANG WU
HONG-SHYANG WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942541Abstract: A semiconductor device including a substrate, a source region, a drain region, a first gate structure and a second gate structure is provided. The source region and a drain region are formed in the substrate. The first gate structure is formed on the substrate and adjacent to the source region. The second gate structure is formed on the substrate and adjacent to the drain region. The second gate structure is electrically coupled to the drain region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20240096975Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Hong-Shyang WU, Kuo-Ming WU
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Publication number: 20240047574Abstract: A semiconductor device includes a first well of a first conductivity type near a surface of a semiconductor substrate, and a second well of a second conductivity type near the surface of the semiconductor substrate. The semiconductor device includes a transistor comprising: (i) a first source/drain region formed in the first well; (ii) a second source/drain region formed in the second well; and (iii) a gate structure formed near the surface of the semiconductor substrate and separated from the second source/drain region at least with a portion of a third well of the second conductive type. The semiconductor device includes an isolation structure formed near the surface of the semiconductor substrate and further separating the second source/drain region from the gate structure. The semiconductor device includes a plurality of field plates formed above at least one of the portion of the third well or the isolation structure.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Patent number: 11855158Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: GrantFiled: March 29, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Patent number: 11848321Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.Type: GrantFiled: April 23, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20230402532Abstract: A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Inventors: Hong-Shyang WU, Kuo-Ming WU
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Publication number: 20230389387Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Patent number: 11832496Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.Type: GrantFiled: May 20, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company LTDInventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20230380238Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20230282525Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.Type: ApplicationFiled: May 19, 2022Publication date: September 7, 2023Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20230275149Abstract: A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.Type: ApplicationFiled: May 23, 2022Publication date: August 31, 2023Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20230061900Abstract: A semiconductor device including a substrate, a source region, a drain region, a first gate structure and a second gate structure is provided. The source region and a drain region are formed in the substrate. The first gate structure is formed on the substrate and adjacent to the source region. The second gate structure is formed on the substrate and adjacent to the drain region. The second gate structure is electrically coupled to the drain region.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: HONG-SHYANG WU, KUO-MING WU
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Publication number: 20220344323Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: HONG-SHYANG WU, KUO-MING WU
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Publication number: 20210217855Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Hong-Shyang WU, Kuo-Ming WU
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Patent number: 10964789Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: GrantFiled: July 26, 2018Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20180337240Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: ApplicationFiled: July 26, 2018Publication date: November 22, 2018Inventors: Hong-Shyang WU, Kuo-Ming WU
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Patent number: 10121867Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: GrantFiled: May 5, 2016Date of Patent: November 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hong-Shyang Wu, Kuo-Ming Wu
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Publication number: 20170194439Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.Type: ApplicationFiled: May 5, 2016Publication date: July 6, 2017Inventors: HONG-SHYANG WU, KUO-MING WU