Abstract: A sampling device and method for evaluating ecological risk of soil in a high geological background area comprises an impact sampling mechanism, a soil layer stripping mechanism and an auxiliary support frame. The impact sampling mechanism comprises a sampling hopper with a downward opening. A connecting sliding rod is fixedly arranged on the top of the sampling hopper. An upper end of the connecting sliding rod is connected with an impact rod. The impact rod is internally provided with an impact hammer capable of reciprocating along an axis of the impact rod. The soil layer stripping mechanism comprises a stripping sliding cylinder in sliding fit with the connecting sliding rod, and a support disc. A plurality of stripping plates are connected to a lower side edge of the support disc in a sliding fit mode.

Abstract: A sampling device and method for evaluating ecological risk of soil in a high geological background area comprises an impact sampling mechanism, a soil layer stripping mechanism and an auxiliary support frame. The impact sampling mechanism comprises a sampling hopper with a downward opening. A connecting sliding rod is fixedly arranged on the top of the sampling hopper. An upper end of the connecting sliding rod is connected with an impact rod. The impact rod is internally provided with an impact hammer capable of reciprocating along an axis of the impact rod. The soil layer stripping mechanism comprises a stripping sliding cylinder in sliding fit with the connecting sliding rod, and a support disc. A plurality of stripping plates are connected to a lower side edge of the support disc in a sliding fit mode.

Abstract: A circuit and a method for removing spread spectrum are provided. The circuit includes a data clock recovery module and a clock extraction module that are connected. The data clock recovery module performs clock recovery on an input signal carrying spread spectrum information to obtain a parallel clock signal and a first signal, where the parallel clock signal includes frequency information and phase information, and the first signal includes the frequency information. The clock extraction module divides a frequency of the parallel clock signal to obtain a reference clock signal; acquires a feedback clock signal based on the first signal; acquires a de-spread clock signal based on the reference clock signal and the feedback clock signal, where the de-spread clock signal includes the phase information and does not include the frequency information; and divides a frequency of the de-spread clock signal to obtain an output clock signal.

Abstract: The present invention relates to a novel compound, which has cancer therapeutic activity. The present invention also relates to a preparation method for the compound and a pharmaceutical composition comprising the compound.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Abstract: A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Abstract: A matrix switcher is provided. A code rate of an ultra-high-definition video signal is reduced on the premise that the quality of the ultra-high-definition video signal is not affected through performing a Color Space Conversion (CSC) process and/or a Digital Stream Compression (DSC) process on the ultra-high-definition video signal at the transmitting side chip, thereby reducing a bandwidth required in conversion, switch and transmission of the ultra-high-definition video signal. A matrix switch chip with a low cost and general performance is used. Then, a corresponding DSC data decompression process and/or CSC process are performed at the receiving side to recover the performance of the ultra-high-definition video signal.

Abstract: A chip is provided, which includes a first receiving module, a protocol logic module, a color space conversion module, a compression module and a transmitting module. The first receiving module is configured to receive a digital video signal. The protocol logic module is configured to perform protocol unpacking on the digital video signal to obtain a video code stream. The color space conversion module is configured to perform color space conversion on the video code stream. The compression module is configured to perform lossless compression on the video code stream obtained by the color space conversion. The transmitting module is configured to transmit the video code stream obtained by the lossless compression.

Abstract: A matrix switcher is provided. A code rate of an ultra-high-definition video signal is reduced on the premise that the quality of the ultra-high-definition video signal is not affected through performing a Color Space Conversion (CSC) process and/or a Digital Stream Compression (DSC) process on the ultra-high-definition video signal at the transmitting side chip, thereby reducing a bandwidth required in conversion, switch and transmission of the ultra-high-definition video signal. A matrix switch chip with a low cost and general performance is used. Then, a corresponding DSC data decompression process and/or CSC process are performed at the receiving side to recover the performance of the ultra-high-definition video signal.

Abstract: A method and a system for encrypting a data stream are provided. The method includes receiving a multimedia data stream including multiple data elements; dividing the multimedia data stream into M data sub-streams based on sequence of the multiple data elements in the multimedia data stream, where the M data sub-streams follow a synchronous clock period which is M times of a clock period of the multimedia data stream, where M is a positive integer greater than 1; and generating a key at a predetermined time interval with a new pipeline algorithm, and encrypting the data elements in the M data sub-streams with the key and the complicated control logic, and the predetermined time interval is N times of the clock period of the M data sub-streams, where N is a positive integer.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Abstract: A method and a system for encrypting a data stream are provided. The method includes receiving a multimedia data stream including multiple data elements; dividing the multimedia data stream into M data sub-streams based on sequence of the multiple data elements in the multimedia data stream, where the M data sub-streams follow a synchronous clock period which is M times of a clock period of the multimedia data stream, where M is a positive integer greater than 1; and generating a key at a predetermined time interval with a new pipeline algorithm, and encrypting the data elements in the M data sub-streams with the key and the complicated control logic, and the predetermined time interval is N times of the clock period of the M data sub-streams, where N is a positive integer.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.