Patents by Inventor Hong-Gyeom Kim
Hong-Gyeom Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110267Abstract: The present invention relates to a steel material for pressure vessels, offshore structures and the like and, more specifically, to a high-strength steel material having excellent low-temperature strain aging impact properties and a method for manufacturing same.Type: ApplicationFiled: December 12, 2023Publication date: April 4, 2024Applicant: POSCO CO., LTDInventors: Kyung-Keun Um, Woo-Gyeom Kim, Hong-Ju Lee
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Patent number: 10762933Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.Type: GrantFiled: November 21, 2018Date of Patent: September 1, 2020Assignee: SK hynix Inc.Inventors: Hong Gyeom Kim, Dae Ho Ra, Byung Kuk Yoon, Min Sik Han
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Publication number: 20190325925Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.Type: ApplicationFiled: November 21, 2018Publication date: October 24, 2019Applicant: SK hynix Inc.Inventors: Hong Gyeom KIM, Dae Ho RA, Byung Kuk YOON, Min Sik HAN
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Patent number: 9530472Abstract: A data alignment device includes a buffer configured to buffer a data strobe signal, output a data strobe pulse signal, and buffer inputted data, a latch configured to latch the data in correspondence to the data strobe pulse signal, a first delay configured to delay the data strobe pulse signal and output a delayed signal, a divider configured to divide the delayed signal at a time of activation of a division control signal and generate a plurality of divided signals, a control circuit configured to receive a command signal, a clock, the data strobe signal, and the plurality of divided signals, and control the division control signal for controlling an enable state of the divider, and an alignment circuit configured to align output data in correspondence to the plurality of divided signals.Type: GrantFiled: June 1, 2016Date of Patent: December 27, 2016Assignee: SK HYNIX INC.Inventors: Min Su Park, Hong Gyeom Kim
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Patent number: 9379701Abstract: A semiconductor device includes a plurality of chips; a first through-chip via vertically passing through the chips, a power-saving unit suitable for being precharged to a precharge voltage during a precharge period; and a driving unit suitable for driving data using the precharge voltage outputted from the power-saving unit, during a driving period.Type: GrantFiled: March 18, 2015Date of Patent: June 28, 2016Assignee: SK Hynix Inc.Inventor: Hong-Gyeom Kim
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Publication number: 20160182070Abstract: An analog-to-digital converter may include a voltage-controlled oscillator suitable for generating an oscillation wave with a frequency corresponding to an input voltage, a counter suitable for counting the activation number of the oscillation wave to generate a digital code, and an operation section setting unit suitable for setting an operation section of at least one of the voltage-controlled oscillator and the counter.Type: ApplicationFiled: June 12, 2015Publication date: June 23, 2016Inventor: Hong-Gyeom KIM
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Patent number: 9362930Abstract: An analog-to-digital converter may include a voltage-controlled oscillator suitable for generating an oscillation wave with a frequency corresponding to an input voltage, a counter suitable for counting the activation number of the oscillation wave to generate a digital code, and an operation section setting unit suitable for setting an operation section of at least one of the voltage-controlled oscillator and the counter.Type: GrantFiled: June 12, 2015Date of Patent: June 7, 2016Assignee: SK Hynix Inc.Inventor: Hong-Gyeom Kim
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Patent number: 9329925Abstract: A transmission/reception system includes first to Nth channels, where N is an integer equal to or greater than 3; a transmission chip suitable for transmitting first to (N?1)th signals through the first to (N?1)th channels and transmitting a correction signal generated by using the first to (N?1)th signals to the Nth channel; and a reception chip suitable for receiving signals of the first to Nth channels and generating restored signals of the first to Nth channels by using the first to Nth channels.Type: GrantFiled: June 12, 2014Date of Patent: May 3, 2016Assignee: SK Hynix Inc.Inventor: Hong-Gyeom Kim
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Publication number: 20160105171Abstract: A semiconductor device includes a plurality of chips; a first through-chip via vertically passing through the chips, a power-saving unit suitable for being precharged to a precharge voltage during a precharge period; and a driving unit suitable for driving data using the precharge voltage outputted from the power-saving unit, during a driving period.Type: ApplicationFiled: March 18, 2015Publication date: April 14, 2016Inventor: Hong-Gyeom KIM
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Patent number: 9202802Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.Type: GrantFiled: February 25, 2014Date of Patent: December 1, 2015Assignee: SK Hynix Inc.Inventors: Heat Bit Park, Jong Chern Lee, Hong Gyeom Kim
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Publication number: 20150180704Abstract: A transmission/reception system includes first to Nth channels, where N is an integer equal to or greater than 3; a transmission chip suitable for transmitting first to (N?1)th signals through the first to (N?1)th channels and transmitting a correction signal generated by using the first to (N?1)th signals to the Nth channel; and a reception chip suitable for receiving signals of the first to Nth channels and generating restored signals of the first to Nth channels by using the first to Nth channels.Type: ApplicationFiled: June 12, 2014Publication date: June 25, 2015Inventor: Hong-Gyeom KIM
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Publication number: 20150115435Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.Type: ApplicationFiled: February 25, 2014Publication date: April 30, 2015Applicant: SK hynix Inc.Inventors: Heat Bit PARK, Jong Chern LEE, Hong Gyeom KIM
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Patent number: 8873313Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.Type: GrantFiled: April 2, 2014Date of Patent: October 28, 2014Assignee: SK Hynix Inc.Inventor: Hong Gyeom Kim
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Publication number: 20140226419Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.Type: ApplicationFiled: April 2, 2014Publication date: August 14, 2014Applicant: SK hynix Inc.Inventor: Hong Gyeom KIM
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Patent number: 8724405Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.Type: GrantFiled: August 30, 2012Date of Patent: May 13, 2014Assignee: SK Hynix Inc.Inventor: Hong Gyeom Kim
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Publication number: 20130279274Abstract: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.Type: ApplicationFiled: August 30, 2012Publication date: October 24, 2013Applicant: SK HYNIX INC.Inventor: Hong Gyeom KIM
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Patent number: 8330527Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.Type: GrantFiled: November 18, 2010Date of Patent: December 11, 2012Assignee: SK Hynix Inc.Inventor: Hong Gyeom Kim
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Publication number: 20110291744Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.Type: ApplicationFiled: November 18, 2010Publication date: December 1, 2011Applicant: Hynix Semiconductor Inc.Inventor: Hong Gyeom KIM
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Publication number: 20110164451Abstract: A semiconductor integrated circuit comprises a plurality of fuses arranged to be spaced apart from one another by predetermined intervals, and a page buffer electrically connected to the plurality of fuses and configured to determine whether to disconnect the fuses. The fuses comprise a NAND flash string. The NAND flash string comprises a drain select transistor connected to a bit line, a flash memory cell electrically connected to the drain select transistor, and a source select transistor connected between the flash memory cell and a ground terminal.Type: ApplicationFiled: July 14, 2010Publication date: July 7, 2011Applicant: Hynix Semiconductor Inc.Inventors: Hong Gyeom KIM, Eun Mi YEON
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Patent number: 7852140Abstract: An internal voltage generation circuit includes a level detection unit configured to generate a detection voltage corresponding to a voltage level difference between a reference voltage with an internal voltage, an oscillation signal generation unit configured to generate an oscillation signal having a period corresponding to a voltage level of the detection voltage, and an internal voltage generation unit configured to generate the internal voltage in response to the oscillation signal.Type: GrantFiled: December 30, 2008Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventors: Do-Yun Lee, Hong-Gyeom Kim