Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Abstract: In one embodiment, an integrated circuit has a conductive layer, where the conductive layer has a first set of regions and a second set of fill material regions, and the second set of fill material regions has a line of symmetry. Other embodiments are described and claimed.

Abstract: A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.

Abstract: A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.

Abstract: Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.

Abstract: Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.

Abstract: Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include portions of multiple blocks. The marker information is used to extract layout information corresponding to the segment. The extracted segment layout information is analyzed to determine the defect prediction information. In one example, the determination involves performing a Critical Area Analysis such that the defect prediction information is a yield prediction value. This process is repeated for multiple segments, and the defect prediction information for the segments is compared to identify the segment most susceptible to defects. The user can modify the design of the segment, and repeat the process to improve yield in the manufacture of the integrated circuit.

Abstract: Metal is deleted from portions of metal wires in an integrated circuit layout, based upon a width of the metal wires. Preliminary cutting forms having a length and a width are inserted with a first orientation in the portions of metal wire. It is determined if the width of each of the preliminary cutting forms is parallel to a width of the metal wire portions where the preliminary cutting forms are inserted. If the preliminary cutting forms have width parallel to the width of the metal wire portion, the preliminary cutting forms become part of a cutting form final layout. Cutting forms not having widths parallel to the width of the metal wire portions are removed. Cutting forms at different orientations are then inserted where the prior cutting forms were removed from and the process repeats until all portions of the metal wire have cutting forms inserted parallel to the current flow direction.

Abstract: In one embodiment, an integrated circuit has a conductive layer, where the conductive layer has a first set of regions and a second set of fill material regions, and the second set of fill material regions has a line of symmetry. Other embodiments are described and claimed.

Abstract: Metal is deleted from portions of metal wires in an integrated circuit layout, based upon a width of the metal wires. Preliminary cutting forms having a length and a width are inserted with a first orientation in the portions of metal wire. It is determined if the width of each of the preliminary cutting forms is parallel to a width of the metal wire portions where the preliminary cutting forms are inserted. If the preliminary cutting forms have width parallel to the width of the metal wire portion, the preliminary cutting forms become part of a cutting form final layout. Cutting forms not having widths parallel to the width of the metal wire portions are removed. Cutting forms at different orientations are then inserted where the prior cutting forms were removed from and the process repeats until all portions of the metal wire have cutting forms inserted parallel to the current flow direction.

Abstract: A method and apparatus for insertion of filling forms within a design layout are described. One or more jog areas are identified within a circuit design layout. Subsequently, multiple filling forms are inserted within the circuit design layout, each filling form being configured to eliminate a corresponding jog area within the circuit design layout. One or more filling forms that violate at least one predetermined design rule applicable to the circuit design layout are identified. The filling forms are then adapted to comply with the predetermined design rule or rules. Finally, remaining filling forms in compliance with the predetermined design rule or rules are combined within the circuit design layout to form a circuit design output layout.

Abstract: A method and apparatus for insertion of filling forms within a design layout are described. One or more jog areas are identified within a circuit design layout. Subsequently, multiple filling forms are inserted within the circuit design layout, each filling form being configured to eliminate a corresponding jog area within the circuit design layout. One or more filling forms that violate at least one predetermined design rule applicable to the circuit design layout are identified. The filling forms are then adapted to comply with the predetermined design rule or rules. Finally, remaining filling forms in compliance with the predetermined design rule or rules are combined within the circuit design layout to form a circuit design output layout.

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: A decoupling capacitor suitable for use with 0.11 micron or less, for example 0.09 micron, CMOS technology is provided herein. The decoupling capacitor includes a decoupling structure that minimizes leakage current associated with the decoupling capacitor.

Abstract: A method and apparatus are provided for depositing a filler material in a physical layout for an integrated circuit. The filler material is deposited on a layer by layer basis in the physical layout so that a channel length of the filler material has an orientation that differs between immediately adjacent layers. In addition, the filler materials in each of the layers are grouped into a first group and a second group wherein the filler material associated with the first group is coupled to a first portion of a power grid in the integrated circuit and the filler material associated with the second group is coupled to a second portion of the power grid in the integrated circuit. The tiller materials associated with each group are interconnected using one or more vias so that the filler material is capable of expanding the power grid of the integrated circuit to assist in the distribution of power throughout the various layers of the integrated circuit.

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.

Abstract: A decoupling capacitor suitable for use with 0.11 micron or less, for example 0.09 micron, CMOS technology is provided herein. The decoupling capacitor includes a decoupling structure that minimizes leakage current associated with the decoupling capacitor.

Abstract: A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.