Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceiver chip through at least a part of an out-bound data path of the transceiver chip, is detected, then a more reliable secondary clock signal is substituted for the primary clock signal. Once it is determined that the primary clock signal has recovered, the primary clock signal is switched back to and certain discrete circuits of the out-bound data path of the transceiver chip are automatically reset in hardware without the need for system level intervention to avoid any problems due to clock glitches on the primary clock signal during the switching.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received.

Abstract: A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

Abstract: Aspects of the invention may include a data transition circuit (600) for formatting data from a first data bus having a first bus width to be compatible with a second data bus having a second bus width. The data transition circuit (600) may include a selector (606) adapted to receive an m-bit input clocked into the selector at a first clock rate from the first data bus. The selector may also be adapted to produce an n-bit output. The selector may include a select signal that may be configured to connect at least a portion of the m-bit input of the selector to the n-bit output of the selector. A first-in-first-out (FIFO) buffer (608) may be coupled to the selector (606) and adapted to buffer the n-bit output of the selector (606). The selector (606) may be configured so that the n-bit output of selector (606) may be clocked into the FIFO buffer at a second clock rate. Additionally, the n-bit output of selector (606) may be clocked out of the FIFO buffer (608) at a second clock rate onto the second data bus.