Patents by Inventor Honorio T. Granada

Honorio T. Granada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for connecting a die attach pad to a lead frame and product thereof
    Patent number: 8110492
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 7, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, Jr., Paul Armand Calo
  • METHOD FOR CONNECTING A DIE ATTACH PAD TO A LEAD FRAME AND PRODUCT THEREOF
    Publication number: 20100304534
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 2, 2010
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, JR., Paul Armand Calo
  • Method for connecting a die attach pad to a lead frame and product thereof
    Patent number: 7800207
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 21, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, Jr., Paul Armand Calo
  • Stacked synchronous buck converter
    Patent number: 7750445
    Abstract: A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: July 6, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Qiuxiao Qian, Honorio T. Granada, Jr.
  • METHOD FOR CONNECTING A DIE ATTACH PAD TO A LEAD FRAME AND PRODUCT THEREOF
    Publication number: 20090102031
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, JR., Paul Armand Calo
  • STACKED SYNCHRONOUS BUCK CONVERTER
    Publication number: 20090072359
    Abstract: A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Yong Liu, Qiuxiao Qian, Honorio T. Granada, JR.
  • Flip chip substrate design
    Patent number: 7101734
    Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: September 5, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Honorio T. Granada, Rajeev Joshi, Connie Tangpuz
  • Flip chip substrate design
    Patent number: 6661082
    Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: December 9, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Honorio T. Granada, Rajeev Joshi, Connie Tangpuz