Abstract: Provided is a display device comprising at least one sensing pixel including a sensing pixel circuit, a sensing unit including sensing circuit, and a temperature output unit to calculate a temperature of the display panel based on the sensing data. The sensing data is generated from a sensing pixel including a driving transistor in which a current generated according to temperature varies, and a temperature is measured from the sensing data.

Abstract: Disclosed are an apparatus and system for evaluating a welding condition on the basis of three-dimensional data. An aspect of the present embodiment provides an apparatus for evaluating a welding condition, the apparatus including a communication unit configured to receive a three-dimensional image for an evaluation target from the outside, a base material recognition unit configured to recognize a base material from the three-dimensional image for the evaluation target by using a point cloud, a bead extraction unit configured to extract a welding bead welded between the base materials, a bead cross-section acquisition unit configured to acquire cross-sections at preset intervals for the extracted welding bead, and a profile analysis unit configured to analyze a profile of the welding bead for the cross-section acquired by the bead cross-section acquisition unit.

Abstract: An electronic device is provided. The electronic device includes an outer housing that comprises a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a side surface surrounding a space between the first surface and the second surface, a display adapted to expose at least a portion of the display through the first surface of the outer housing, a PCB arranged between the second surface and the display in an interior of the outer housing, a communication circuit arranged on or over the PCB, a first conductive structure formed of at least one of the first surface or at least a portion of the side surface is electrically connected to the communication circuit, and a second conductive structure formed of the portion of the display electrically connected to the first conductive structure.

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.

Abstract: Lactobacillus plantarum CJLP243 (KCTC 11045P), a composition for treating intestinal diseases comprising Lactobacillus plantarum CJLP243, and a composition for enhancing immune response comprising Lactobacillus plantarum CJLP243.

Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.

Abstract: An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Abstract: Provided is an apparatus for measuring a depth with a pseudo 4-tap pixel structure, the apparatus including a delta sigma circuit configured to calculate, through a delta sigma operation, a delta value of a first angle corresponding to a first row line of a pixel array for measuring a depth of an object and calculate, through a delta sigma operation, a delta value of a third angle corresponding to a second row line of the pixel array, a memory configured to store the calculated delta value of the first angle corresponding to the first row line, and an arithmetic logic unit (ALU) configured to compute depth information corresponding to the first row line by using the stored delta value of the first angle corresponding to the first row line and the calculated delta value of the third angle corresponding to the second row line.

Abstract: An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.

Abstract: A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

Abstract: A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

Abstract: Lactobacillus plantarum CJLP243 (KCTC 11045P), a composition for treating intestinal diseases comprising Lactobacillus plantarum CJLP243, and a composition for enhancing immune response comprising Lactobacillus plantarum CJLP243.

Abstract: Provided are a CIS system and a method of processing the same using a low power multi-mode data path. In order to drive a circuit with low-power, the CMOS Image Sensor (CIS) system rearranges and transmits data in consideration of a color of pixel data and a most significant bit (MSB) and a least significant bit (LSB) of the pixel data using a low-power multi-mode data path. The CIS system can implement multi-modes including a low power mode and a high speed mode, reduce the number of data transitions by merging data of the same color in a always-on low-power mode and a photo-shooting low-power (PS-LP) mode to reduce power consumption and process data in a high speed using a pipeline in a photo-shooting high-speed (PS-HS) mode.

Abstract: An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.