Abstract: A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

Abstract: A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

Abstract: A non-glasses type stereoscopic image display device comprises: a display panel that comprises a plurality of sub-pixels and displays multi-view images in predetermined units; and an optical plate array that is formed side by side with the sub-pixels and divides the multi-view images into a plurality of multi-view areas, each of the sub-pixels comprising a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, which alternate in the same row along a horizontal direction in which gate lines extend and are formed side by side along a vertical direction in which data lines extend in different columns, wherein vertically neighboring sub-pixels displaying different colors partially overlap each other in the vertical direction.

Abstract: An autostereoscopic display and a control method thereof are disclosed. The autostereoscopic display includes a display panel displaying 3D image data, a backlight unit providing light to the display panel, a backlight driver which sequentially drives light sources of the backlight unit along a scanning direction of the 3D image data written to the display panel, a switchable 3D element which forms a barrier or a lens for separating optical axes of left eye image data and right eye image data from the 3D image data, and a 3D element driver which electrically controls the switchable 3D element and shifts the barrier or the lens formed in the switchable 3D element.

Abstract: A non-glasses type stereoscopic image display device comprises: a display panel that comprises a plurality of sub-pixels and displays multi-view images in predetermined units; and an optical plate array that is formed side by side with the sub-pixels and divides the multi-view images into a plurality of multi-view areas, each of the sub-pixels comprising a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, which alternate in the same row along a horizontal direction in which gate lines extend and are formed side by side along a vertical direction in which data lines extend in different columns, wherein vertically neighboring sub-pixels displaying different colors partially overlap each other in the vertical direction.

Abstract: An autostereoscopic display and a control method thereof are disclosed. The autostereoscopic display includes a display panel displaying 3D image data, a backlight unit providing light to the display panel, a backlight driver which sequentially drives light sources of the backlight unit along a scanning direction of the 3D image data written to the display panel, a switchable 3D element which forms a barrier or a lens for separating optical axes of left eye image data and right eye image data from the 3D image data, and a 3D element driver which electrically controls the switchable 3D element and shifts the barrier or the lens formed in the switchable 3D element.