Abstract: The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.

Abstract: A voltage clamping circuit for protecting an internal circuitry comprising an input means for receiving Vin; a p-channel clamping transistor (PCT) coupled to input means for clamping Vin to prevent Vin from falling below a p-channel biasing voltage VbiasP; an n-channel clamping transistor (NCT) coupled to input means for clamping Vin to prevent Vin from rising above an n-channel biasing voltage VbiasN; and a plurality of output means for providing a first output voltage from PCT and a second output voltage from NCT; a p-channel bias circuit including a first, a second and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on PCT; and an n-channel bias circuit including a fourth, a fifth and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on NCT.

Abstract: A voltage clamping circuit for protecting an internal circuitry comprising an input means for receiving Vin; a p-channel clamping transistor (PCT) coupled to input means for clamping Vin to prevent Vin from falling below a p-channel biasing voltage VbiasP; an n-channel clamping transistor (NCT) coupled to input means for clamping Vin to prevent Vin from rising above an n-channel biasing voltage VbiasN; and a plurality of output means for providing a first output voltage from PCT and a second output voltage from NCT; a p-channel bias circuit including a first, a second and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on PCT; and an n-channel bias circuit including a fourth, a fifth and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on NCT.

Abstract: An apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystem. The apparatus includes a plurality of end-of-transfer detection flip-flops configured to sample a read data enable signal; a flag flip-flop; a first logic circuit configured to generate a load enable signal in response to the end-of-transfer detection flip-flops and the flag flip-flop; a second logic circuit configured to generate a load data in response to the end-of-transfer detection flip-flops, the flag flip-flop and the read data enable signal; a plurality of first-in-first-out buffers configured to receive the load enable signal and the load data, and unload the load data as an end-of-transfer indicator in line with data strobe; and a plurality of bypass flip-flops configured to generate a bypass signal in response to the end-of-transfer indicator.

Abstract: Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.

Abstract: An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.

Abstract: Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.

Abstract: A termination circuit includes a first transistor coupled to a first pad, a first resistor coupled between the first transistor and a second pad, and an operational amplifier circuit. The termination circuit provides termination impedance to input signals received at the first and second pads. The first transistor generates a first common mode voltage of the input signals at a first node between the first resistor and the first transistor in response to an output signal of the operational amplifier circuit. The operational amplifier circuit generates the output signal based on the first common mode voltage of the input signals and based on a second common mode voltage of the input signals. The termination circuit generates the second common mode voltage at a second node that is a different node than the first node.

Abstract: An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The first resistive path circuit may generate a first common mode voltage from the differential signals. The feedback circuit is coupled to the first resistive path circuit. The feedback circuit receives the first common mode voltage as an input. The second resistive path circuit includes a transistor circuit and a resistor formed in a serial circuit configuration. The second resistive path circuit may generate a second common mode voltage on a node formed between the transistor circuit and the resistor by controlling activation of the transistor circuit using outputs from the feedback circuit. The first common mode voltage may be substantially identical to the second common mode voltage.

Abstract: An integrated circuit with input voltage clamping circuitry for receiving an input signal from external devices is provided. The input voltage clamping circuitry may include a voltage splitting and clamping circuit, a selectively enabled transmission gate circuit, and a digitization and clamping circuit. The voltage splitting and clamping circuit may be configured to split the input signal into at least two separate components each of which is limited to a predetermined voltage swing. The transmission gate circuit may be selectively enabled to provide full rail signaling when the input signal has a power supply level that is below a predefined threshold. The digitization and clamping circuit may include a Schmitt trigger translation for converting the split signal components to a digitized signal that is clamped down to the predefined threshold.