Patents by Inventor Hoon Sung CHOI
Hoon Sung CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942480Abstract: A semiconductor device includes: a substrate; a first buried insulation layer disposed on the substrate; a first well which is disposed on the first buried insulation layer in a first region defined by a first element separation film, and includes a first portion extending along an upper surface of the first buried insulation layer, and a second portion extending from the first portion in a direction from the substrate toward the first buried insulation layer; a second buried insulation layer disposed on the first portion of the first well; a first semiconductor film disposed on the second buried insulation layer; a first transistor on the first semiconductor film; and a second element separation film which separates the second buried insulation layer and the first semiconductor film from the second portion of the first well, on the first portion of the first well, wherein an upper surface of the second portion of the first well is placed on the same plane as an upper surface of the first element separation fType: GrantFiled: February 10, 2022Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il Min Lee, Hoon-Sung Choi
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Patent number: 11784254Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.Type: GrantFiled: December 22, 2021Date of Patent: October 10, 2023Inventor: Hoon-Sung Choi
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Publication number: 20220320142Abstract: A semiconductor device includes: a substrate; a first buried insulation layer disposed on the substrate; a first well which is disposed on the first buried insulation layer in a first region defined by a first element separation film, and includes a first portion extending along an upper surface of the first buried insulation layer, and a second portion extending from the first portion in a direction from the substrate toward the first buried insulation layer; a second buried insulation layer disposed on the first portion of the first well; a first semiconductor film disposed on the second buried insulation layer; a first transistor on the first semiconductor film; and a second element separation film which separates the second buried insulation layer and the first semiconductor film from the second portion of the first well, on the first portion of the first well, wherein an upper surface of the second portion of the first well is placed on the same plane as an upper surface of the first element separation fType: ApplicationFiled: February 10, 2022Publication date: October 6, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il Min LEE, Hoon-Sung CHOI
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Publication number: 20220115538Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventor: Hoon-Sung Choi
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Patent number: 11239362Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.Type: GrantFiled: May 15, 2019Date of Patent: February 1, 2022Inventor: Hoon-Sung Choi
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Patent number: 11075233Abstract: A semiconductor device and a fabricating method of the same are provided. The semiconductor device a substrate including an active region defined by an element isolation film, an impurity region having a first conductivity type in the active region, a first semiconductor film of a second conductivity type on the impurity region, a buried insulating film on the first semiconductor film, a second semiconductor film on the buried insulating film, and a well contact connected to the first semiconductor film. The level of a lowermost surface of the first semiconductor film is higher than a level of a lowermost surface of the element isolation film.Type: GrantFiled: January 5, 2018Date of Patent: July 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Hoon Sung Choi
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Patent number: 10832939Abstract: A semiconductor comprises two transistors of the first conductivity type separated from two transistors of a second conductivity type by a first element isolation layer. Further, the two transistors of the first conductivity type are separated from each other by a second element isolation layer and the two transistors of the second conductivity type are separated from each other by a third element isolation layer. In example embodiments, the second and third element isolation layers are shallower than the first element isolation layer.Type: GrantFiled: February 14, 2019Date of Patent: November 10, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Hoon-Sung Choi
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Patent number: 10707234Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.Type: GrantFiled: November 29, 2018Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon-Sung Choi, Dong-Il Park, Yuri Masuoka
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Publication number: 20190393348Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.Type: ApplicationFiled: May 15, 2019Publication date: December 26, 2019Inventor: Hoon-Sung Choi
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Publication number: 20190348438Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.Type: ApplicationFiled: November 29, 2018Publication date: November 14, 2019Inventors: Hoon-Sung CHOI, Dong-IL PARK, Yuri MASUOKA
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Publication number: 20190318956Abstract: A semiconductor comprises two transistors of the first conductivity type separated from two transistors of a second conductivity type by a first element isolation layer. Further, the two transistors of the first conductivity type are separated from each other by a second element isolation layer and the two transistors of the second conductivity type are separated from each other by a third element isolation layer. In example embodiments, the second and third element isolation layers are shallower than the first element isolation layer.Type: ApplicationFiled: February 14, 2019Publication date: October 17, 2019Applicant: Samsung Electronics Co., Ltd.Inventor: Hoon-Sung CHOI
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Publication number: 20180374880Abstract: A semiconductor device and a fabricating method of the same are provided. The semiconductor device a substrate including an active region defined by an element isolation film, an impurity region having a first conductivity type in the active region, a first semiconductor film of a second conductivity type on the impurity region, a buried insulating film on the first semiconductor film, a second semiconductor film on the buried insulating film, and a well contact connected to the first semiconductor film. The level of a lowermost surface of the first semiconductor film is higher than a level of a lowermost surface of the element isolation film.Type: ApplicationFiled: January 5, 2018Publication date: December 27, 2018Applicant: Samsung Electronics Co, Ltd.Inventor: Hoon Sung CHOI