Abstract: A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes.

Abstract: A multitasking data processing machine supports virtual memory comprising a plurality of segments, and has physical memory comprising relatively fast main memory and relatively slow secondary memory. A constantly varying subset of secondary memory paged contents is copied in main memory page frames. When a memory access is required during operation of the machine, a virtual address is generated, which must be translated into a physical address, in order to address main memory. The data processing machine provides an indexed local random access memory (T/RAM) for storing previously translated addresses. The T/RAM has a capacity of one entry for each page of supported virtual memory. Before a translation is performed, the T/RAM is indexed by the virtual address; in case of a T/RAM fault, translation is performed and the translated physical address is loaded to the indexed location before restarting the memory operation.