Patents by Inventor Horacio P. Gasquet
Horacio P. Gasquet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9449713Abstract: A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.Type: GrantFiled: June 26, 2012Date of Patent: September 20, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Horacio P. Gasquet, Brian A. Winstead
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Patent number: 9424176Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.Type: GrantFiled: February 25, 2013Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ross S. Scouller, Jeffrey C. Cunningham, Horacio P. Gasquet
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Patent number: 9111639Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.Type: GrantFiled: April 30, 2013Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Horacio P. Gasquet, Ronald J. Syzdek
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Patent number: 8897073Abstract: A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the memory cells, and an erase mode to provide a second voltage that has inverse polarity of the first voltage.Type: GrantFiled: September 14, 2012Date of Patent: November 25, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Horacio P. Gasquet, Jeffrey C. Cunningham
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Publication number: 20140321213Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Inventors: CHEONG MIN HONG, Horacio P. Gasquet, Ronald J. Syzdek
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Publication number: 20140244895Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ross S. Scouller, Jeffrey C. Cunningham, Horacio P. Gasquet
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Patent number: 8793558Abstract: Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.Type: GrantFiled: August 27, 2012Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jeffrey C. Cunningham, Horacio P. Gasquet, Ross S. Scouller, Marco A. Cabassi
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Publication number: 20140078828Abstract: A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the memory cells, and an erase mode to provide a second voltage that has inverse polarity of the first voltage.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventors: Horacio P. GASQUET, Jeffrey C. CUNNINGHAM
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Publication number: 20140059398Abstract: Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.Type: ApplicationFiled: August 27, 2012Publication date: February 27, 2014Inventors: Jeffrey C. Cunningham, Horacio P. Gasquet, Ross S. Scouller, Marco A. Cabassi
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Publication number: 20130343112Abstract: A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Inventors: HORACIO P. GASQUET, BRIAN A. WINSTEAD
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Patent number: 8035156Abstract: A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.Type: GrantFiled: September 30, 2008Date of Patent: October 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Gowrishankar L. Chindalore, Konstantin V. Loiko, Horacio P. Gasquet
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Patent number: 7799634Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.Type: GrantFiled: December 19, 2008Date of Patent: September 21, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Jinmiao J. Shen, Horacio P. Gasquet, Sung-Taeg Kang, Marc A. Rossow
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Patent number: 7782664Abstract: An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.Type: GrantFiled: May 30, 2008Date of Patent: August 24, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Horacio P. Gasquet, Richard K. Eguchi, Peter J. Kuhn, Ronald J. Syzdek
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Publication number: 20100159651Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.Type: ApplicationFiled: December 19, 2008Publication date: June 24, 2010Inventors: Jinmiao J. Shen, Horacio P. Gasquet, Sung-Taeg Kang, Marc A. Rossow
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Publication number: 20100078703Abstract: A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Brian A. Winstead, Gowrishankar L. Chindalore, Konstantin V. Loiko, Horacio P. Gasquet
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Publication number: 20090296464Abstract: An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Horacio P. Gasquet, Richard K. Eguchi, Peter J. Kuhn, Ronald J. Syzdek
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Patent number: 7583542Abstract: A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected word line. This may prevent unintended, program, read, or erase of said unselected word line. The remainder of unselected word lines can be floated.Type: GrantFiled: March 28, 2006Date of Patent: September 1, 2009Assignee: Freescale Semiconductor Inc.Inventor: Horacio P. Gasquet