Patents by Inventor Horia Cristian Simionescu
Horia Cristian Simionescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169232Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.Type: GrantFiled: February 19, 2016Date of Patent: January 1, 2019Assignee: Seagate Technology LLCInventors: Horia Cristian Simionescu, Balakrishnan Sundararaman, Shashank Nemawarkar, Larry Stephen King, Mark Ish, Shailendra Aulakh
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Patent number: 9910798Abstract: Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage controller. The storage controller includes an interface operable to receive Input/Output (I/O) requests from a host, a Direct Memory Access (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.Type: GrantFiled: October 5, 2015Date of Patent: March 6, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Horia Cristian Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
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Patent number: 9910797Abstract: Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory storing data for a logical volume, and a control unit. The control unit is able to service an Input/Output (I/O) request based on a Scatter Gather List (SGL) that refers to the cache memory, the SGL comprising multiple entries that each include a flag field and an identifier (ID) field. The entries are assigned to categories that are each associated with a different set of stored processing instructions. The control unit is able to identify a category for an entry based on a combination of both flag field and ID field for the entry, and the control unit is able to process the entry using the set of instructions associated with the identified category.Type: GrantFiled: October 5, 2015Date of Patent: March 6, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Horia Cristian Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
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Patent number: 9841902Abstract: Systems and methods presented herein provide for SSD data storage via PCIe controllers configured with NVMe interfaces. In one embodiment, a PCIe controller includes a plurality of buffers, a Dynamic Random Access Memory (DRAM) device, and an I/O processor operable to partition the DRAM device into a plurality of logical blocks. The controller also includes virtual function logic communicatively coupled to the logical blocks of the DRAM device and to the buffers. The virtual function logic is coupled to a host system through the I/O processor to process an I/O request from the host system to a logical block of the DRAM device, to retrieve data from the logical block to at least one of the buffers, and to transfer the data from the buffer to the host system.Type: GrantFiled: November 20, 2014Date of Patent: December 12, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Anant Baderdinni, Horia Cristian Simionescu
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Publication number: 20170242794Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Inventors: Horia Cristian Simionescu, Balakrishnan Sundararaman, Shashank Nemawarkar, Larry Stephen King, Mark Ish, Shailendra Aulakh
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Publication number: 20170097909Abstract: Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage controller. The storage controller includes an interface operable to receive Input/Output (I/O) requests from a host, a Direct Memory Access (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.Type: ApplicationFiled: October 5, 2015Publication date: April 6, 2017Inventors: Horia Cristian Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
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Publication number: 20170097908Abstract: Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory storing data for a logical volume, and a control unit. The control unit is able to service an Input/Output (I/O) request based on a Scatter Gather List (SGL) that refers to the cache memory, the SGL comprising multiple entries that each include a flag field and an identifier (ID) field. The entries are assigned to categories that are each associated with a different set of stored processing instructions. The control unit is able to identify a category for an entry based on a combination of both flag field and ID field for the entry, and the control unit is able to process the entry using the set of instructions associated with the identified category.Type: ApplicationFiled: October 5, 2015Publication date: April 6, 2017Inventors: Horia Cristian Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
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Patent number: 9524107Abstract: Methods and structure for host-side device drivers for Redundant Array of Independent Disks (RAID) systems. One system includes a processor and memory of a host, which implement a device driver. The device driver receives an Input/Output (I/O) request from an Operating System (OS) of the host, translates Logical Block Addresses (LBAs) from the received request into physical addresses at multiple storage devices, generates child I/O requests directed to the physical addresses based on the received request, and accesses an address lock system at a RAID controller to determine whether the physical addresses are accessible. If the physical addresses are accessible, the device driver reserves the physical addresses by updating the address lock system, and directs the child I/O requests to a hardware path at the RAID controller for handling single-strip I/O requests. If the physical addresses are not accessible, the device driver delays processing of the child I/O requests.Type: GrantFiled: July 30, 2014Date of Patent: December 20, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Adam Weiner, James A Rizzo, Mark Ish, Robert L Sheffield, Horia Cristian Simionescu
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Publication number: 20160283379Abstract: Methods and structure for utilizing linked lists to flush a cache. One exemplary embodiment includes a memory, an interface, and an Input/Output (I/O) processor. The memory implements a cache divided into cache lines, and the interface receives I/O directed to a block address of a storage device. The I/O processor determines a remainder by dividing the block address by the number of cache lines, and selects a cache line for storing the I/O based on the remainder. The I/O processor determines a quotient by dividing the block address by the number of cache lines, and associates the quotient with the selected cache line. Additionally, the I/O processor populates a linked list by inserting entries that each point to a different cache line associated with the same quotient, and flushes the cache lines to the storage device in block address order by traversing the entries of the linked list.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Sumanesh Samanta, Horia Cristian Simionescu, Ashish Jain
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Publication number: 20160147442Abstract: Systems and methods presented herein provide for SSD data storage via PCIe controllers configured with NVMe interfaces. In one embodiment, a PCIe controller includes a plurality of buffers, a Dynamic Random Access Memory (DRAM) device, and an I/O processor operable to partition the DRAM device into a plurality of logical blocks. The controller also includes virtual function logic communicatively coupled to the logical blocks of the DRAM device and to the buffers. The virtual function logic is coupled to a host system through the I/O processor to process an I/O request from the host system to a logical block of the DRAM device, to retrieve data from the logical block to at least one of the buffers, and to transfer the data from the buffer to the host system.Type: ApplicationFiled: November 20, 2014Publication date: May 26, 2016Inventors: Anant Baderdinni, Horia Cristian Simionescu
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Patent number: 9292204Abstract: A system and method for managing cache memory of at least one node of a multiple-node storage cluster. A first cache data and a first cache metadata are stored for data transfers between a respective node and regions of a storage cluster receiving at least a first selected number of data transfer requests. When the node is rebooted, a second (new) cache data is stored to replace the first (old) cache data. The second cache data is compiled utilizing the first cache metadata to identify previously cached regions of the storage cluster receiving at least a second selected number of data transfer requests after the node is rebooted. The second selected number of data transfer requests is less than the first selected number of data transfer requests to enable a rapid build of the second cache data.Type: GrantFiled: June 25, 2013Date of Patent: March 22, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Sumanesh Samanta, Sujan Biswas, Horia Cristian Simionescu, Luca Bert, Mark Ish
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Patent number: 9286175Abstract: The disclosure is directed to preserving data consistency in a multiple-node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a full write journal of data and parity associated with each data transfer request, the log entries only need to identify portions of the virtual volume being updated according to the data transfer requests served by each node. When a first node fails, a second node takes over administration of a virtual volume for the failed node. Upon taking over for the first (failed) node, the second node resolves any inconsistencies between data and parity in portions of the virtual volume identified the respective log entries. Accordingly, write holes are prevented without substantially increasing memory usage or system complexity.Type: GrantFiled: November 27, 2013Date of Patent: March 15, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Sumanesh Samanta, Horia Cristian Simionescu, Luca Bert, Debal Kr. Mridha, Mohana Rao Goli
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Patent number: 9268695Abstract: Methods and structure within a storage controller for using region locks to efficiently divert an I/O request received from an attached host system to one of multiple processing stacks in the controller. A region lock module within the controller allows each processing stack to request a region lock for a range of block addresses of the storage devices. A divert-type lock request may be established to identify a range of block addresses for which I/O requests should be diverted to a particular one of the multiple processing stacks.Type: GrantFiled: December 12, 2012Date of Patent: February 23, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Adam Weiner, Robert L. Sheffield, Jr., Naveen Krishnamurthy, Kapil Sundrani, Rajeev Srinivasa Murthy, Anand Narayanamurthy, Horia Cristian Simionescu, James A. Rizzo
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Publication number: 20160034186Abstract: Methods and structure for host-side device drivers for Redundant Array of Independent Disks (RAID) systems. One system includes a processor and memory of a host, which implement a device driver. The device driver receives an Input/Output (I/O) request from an Operating System (OS) of the host, translates Logical Block Addresses (LBAs) from the received request into physical addresses at multiple storage devices, generates child I/O requests directed to the physical addresses based on the received request, and accesses an address lock system at a RAID controller to determine whether the physical addresses are accessible. If the physical addresses are accessible, the device driver reserves the physical addresses by updating the address lock system, and directs the child I/O requests to a hardware path at the RAID controller for handling single-strip I/O requests. If the physical addresses are not accessible, the device driver delays processing of the child I/O requests.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Applicant: LSI CORPORATIONInventors: Adam Weiner, James A Rizzo, Mark Ish, Robert L Sheffield, Horia Cristian Simionescu
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Patent number: 9058274Abstract: The disclosure is directed to a system and method for managing READ cache memory of at least one node of a multiple-node storage cluster. According to various embodiments, a cache data and a cache metadata are stored for data transfers between a respective node (hereinafter “first node”) and regions of a storage cluster. When the first node is disabled, data transfers are tracked between one or more active nodes of the plurality of nodes and cached regions of the storage cluster. When the first node is rebooted, at least a portion of valid cache data is retained based upon the tracked data transfers. Accordingly, local cache memory does not need to be entirely rebuilt each time a respective node is rebooted.Type: GrantFiled: June 24, 2013Date of Patent: June 16, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Sumanesh Samanta, Sujan Biswas, Horia Cristian Simionescu, Luca Bert, Mark Ish
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Publication number: 20150135006Abstract: The disclosure is directed to preserving data consistency in a multiple-node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a full write journal of data and parity associated with each data transfer request, the log entries only need to identify portions of the virtual volume being updated according to the data transfer requests served by each node. When a first node fails, a second node takes over administration of a virtual volume for the failed node. Upon taking over for the first (failed) node, the second node resolves any inconsistencies between data and parity in portions of the virtual volume identified the respective log entries. Accordingly, write holes are prevented without substantially increasing memory usage or system complexity.Type: ApplicationFiled: November 27, 2013Publication date: May 14, 2015Applicant: LSI CorporationInventors: Sumanesh Samanta, Horia Cristian Simionescu, Luca Bert, Debal Kr. Mridha, Mohana Rao Goli
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Publication number: 20140351523Abstract: The disclosure is directed to a system and method for managing cache memory of at least one node of a multiple-node storage cluster. According to various embodiments, a first cache data and a first cache metadata are stored for data transfers between a respective node and regions of a storage cluster receiving at least a first selected number of data transfer requests. When the node is rebooted, a second (new) cache data is stored to replace the first (old) cache data. The second cache data is compiled utilizing the first cache metadata to identify previously cached regions of the storage cluster receiving at least a second selected number of data transfer requests after the node is rebooted. The second selected number of data transfer requests is less than the first selected number of data transfer requests to enable a rapid build of the second cache data.Type: ApplicationFiled: June 25, 2013Publication date: November 27, 2014Inventors: Sumanesh Samanta, Sujan Biswas, Horia Cristian Simionescu, Luca Bert, Mark Ish
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Publication number: 20140344523Abstract: The disclosure is directed to a system and method for managing READ cache memory of at least one node of a multiple-node storage cluster. According to various embodiments, a cache data and a cache metadata are stored for data transfers between a respective node (hereinafter “first node”) and regions of a storage cluster. When the first node is disabled, data transfers are tracked between one or more active nodes of the plurality of nodes and cached regions of the storage cluster. When the first node is rebooted, at least a portion of valid cache data is retained based upon the tracked data transfers. Accordingly, local cache memory does not need to be entirely rebuilt each time a respective node is rebooted.Type: ApplicationFiled: June 24, 2013Publication date: November 20, 2014Inventors: Sumanesh Samanta, Sujan Biswas, Horia Cristian Simionescu, Luca Bert, Mark Ish
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Publication number: 20140164715Abstract: Methods and structure within a storage controller for using region locks to efficiently divert an I/O request received from an attached host system to one of multiple processing stacks in the controller. A region lock module within the controller allows each processing stack to request a region lock for a range of block addresses of the storage devices. A divert-type lock request may be established to identify a range of block addresses for which I/O requests should be diverted to a particular one of the multiple processing stacks.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: LSI CorporationInventors: Adam Weiner, Robert L. Sheffield, JR., Naveen Krishnamurthy, Kapil Sundrani, Rajeev Srinivasa Murthy, Anand Narayanamurthy, Horia Cristian Simionescu, James A. Rizzo
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Patent number: 8656059Abstract: Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined to encode a sub-tag value. One or more sub-tag values are reserved to indicate that the corresponding read or write command is related to the exchange of administrative information rather than the reading or writing of data on a storage device. A parameter value encoded in the LBA field or data length field of the read or write command indicates administrative data to be returned to the initiator or to be updated within the target device.Type: GrantFiled: May 31, 2012Date of Patent: February 18, 2014Assignee: LSI CorporationInventor: Horia Cristian Simionescu