Abstract: A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.

Abstract: A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.

Abstract: A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources.

Abstract: A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: An interface between a programming system and a set of headphones allows the transmission of both audio and digital data over analog audio signal lines of the headphones. Circuitry on the programming system is configured to transmit digital data over the analog audio signal lines by either modulating a carrier frequency with the digital data such that the digital data is transmitted over non-audible frequencies or by time-multiplexing the transmission of digital data and analog audio data. Circuitry on the headphones is configured to receive digital data by demodulating the modulated digital data or by de-multiplexing the time-multiplexed digital and analog audio data. In other embodiments of acoustic headphones which include microphones, a Talk-Through functionality may be implemented.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: A voltage integrator circuit and a filter circuit are configurable to adjust their outputs in order to compensate for various circuit elements' variations with temperature. The voltage integrator circuit performs temperature compensation through the adjustment in resistance value of a single resistive element in response to a received control signal. The control signal correlates with a detected temperature value and causes the resistive element to adjust its resistance value in a manner that maintains the transfer function of the voltage integrator circuit under varying temperatures. The filter circuit comprises one or more of the voltage integrator circuits and maintains its transfer function under varying temperatures.

Abstract: A test signal generator provides a test signal to an acoustic device under test and a data acquisition device acquires data from the acoustic device. The initial frequency response of the signal path through the acoustic device is determined based on the test signal and the acquired data. A target frequency response is selected. A desired configuration of a configurable circuit in the signal path is determined modifying the signal path such that the frequency response of the signal path is substantially similar to the target frequency response. At least one parameter for at least one programmable component of the configurable circuit is determined and programmed into the programmable component.

Abstract: A spread-spectrum phase-locked loop clock generator includes a PLL circuit, a modulation generator, a bit stream processor and a multiplexer. The modulation generator outputs a bitstream in response to an input signal and a control signal. The bitstream processor generates bitstream signals. The multiplexer outputs one of the bitstream signals in response to a frequency deviation control signal. The PLL circuit is controlled by the output of the multiplexer.

Abstract: A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.

Abstract: A spread-spectrum phase-locked loop clock generator includes a PLL circuit, a modulation generator, a bit stream processor and a multiplexer. The modulation generator outputs a bitstream in response to an input signal and a control signal. The bitstream processor generates bitstream signals. The multiplexer outputs one of the bitstream signals in response to a frequency deviation control signal. The PLL circuit is controlled by the output of the multiplexer.

Abstract: A transconductance-capacitance filter having a plurality of transconductors, that operates in a normal operation mode and a testing/tuning operation mode. During the normal operation mode, the transconductors operate as having normal transconductances. During the testing/tuning operation mode, the transconductances are scaled by a same amount, so that frequencies of the test signals provided are lower than in the normal operation mode, and so that transfer characteristics of the filter can be easily verified.

Abstract: A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.

Abstract: A transconductance-capacitance filter having a plurality of transconductors, that operates in a normal operation mode and a testing/tuning operation mode. During the normal operation mode, the transconductors operate as having normal transconductances. During the testing/tuning operation mode, the transconductances are scaled by a same amount, so that frequencies of the test signals provided are lower than in the normal operation mode, and so that transfer characteristics of the filter can be easily verified.

Abstract: An amplifier is provided The amplifier includes an input voltage-to-current converter, a programmable input current divider, a current follower, a feedback voltage-to-current converter, and a programmable feedback current divider. The input voltage-to-current converter receives an input voltage and provides upper and lower input currents. The input current divider receives a first bias voltage and the upper and lower input currents, scales the upper and lower input currents, and provides upper and lower scaled input currents. The current follower receives the upper and lower scaled input currents, and provides upper and lower output currents and an output voltage. The feedback voltage-to-current converter receives the output voltage and provides upper and lower feedback currents. And the feedback current divider receives a second bias voltage and the upper and lower feedback currents, scales the upper and lower feedback currents, and provides upper and lower scaled feedback currents to the current follower.

Abstract: A cascode transconductor circuit controls the transconductance of a differential stage with an active load followed by a cascode or folded-cascode current follower in discrete steps. The circuit includes a transconductor receiving first and second input voltages, and outputting first and second internal currents, a first resistive divider receiving the first internal current at a digitally-selected first node, and generating a third internal current at a third node, a second resistive divider receiving the second internal current at a digitally-selected second node, and generating a fourth internal current at a fourth node, and a cascode circuit receiving the third and fourth internal currents and supplying first and second output currents.

Abstract: A precision bias is provided for a differential transconductor. The precision bias includes a bias circuit, a differential amplifier and a current mirror. The current mirror includes at least two mirror transistors, one of which is connected to the bias circuit, and th other of which is connected to the differential amplifier. The bias circuit provides a bias current, which the current mirror accurately reflects to the differential amplifier as a tail current. By providing identical operating conditions to the bias circuit and first mirror transistor as are seen at the differential amplifier and second mirror transistor, the precision bias can more accurately reflect the bias current into the tail current. This can reduce the DC output currents of the differential amplifier to substantially zero, which improves its performance. A second bias circuit provides the gate-source voltage of the two transistors forming the load of the differential transconductor.