Patents by Inventor Hormazdyar Minocher Dalal
Hormazdyar Minocher Dalal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7947592Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.Type: GrantFiled: January 31, 2008Date of Patent: May 24, 2011Assignee: Semiconductor Components Industries, LLCInventors: Hormazdyar Minocher Dalal, Jagdish Prasad, Hocine Bouzid Ziad
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Patent number: 7800239Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.Type: GrantFiled: January 31, 2008Date of Patent: September 21, 2010Assignee: Semiconductor Components Industries, LLCInventors: Hormazdyar Minocher Dalal, Jagdish Prasad, Hocine Bouzid Ziad
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Publication number: 20090152725Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.Type: ApplicationFiled: January 31, 2008Publication date: June 18, 2009Applicant: AMI Semiconductor, Inc.Inventors: Hormazdyar Minocher Dalal, Jagdish Prasad, Hocine Bouzid Ziad
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Publication number: 20090152100Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.Type: ApplicationFiled: January 31, 2008Publication date: June 18, 2009Applicant: AMI Semiconductor, Inc.Inventors: Hormazdyar Minocher Dalal, Jagdish Prasad, Hocine Bouzid Ziad
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Patent number: 7163883Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: October 27, 2003Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Patent number: 6734090Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: February 20, 2002Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20040087078Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: October 27, 2003Publication date: May 6, 2004Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20030157794Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: February 20, 2002Publication date: August 21, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Patent number: 6597067Abstract: An interconnection wiring structure in an integrated circuit chip designed to eliminate electromigration. The structure includes segments of aluminum interspersed with segments of refractory metal, wherein each aluminum segment is followed by a segment of refractory metal. The aluminum and refractory metal segments are aligned with respect to each other to ensure electrical continuity and to force the electrical current to sequentially cross the aluminum and the refractory metal segments. The above structure can be advantageously enhanced by adding an underlayer, an overlayer or both, all of which are made of refractory metal. The interconnection wire structure described above can be expanded to include vias or studs linking interconnection lines placed at different levels of the IC chip.Type: GrantFiled: April 17, 1997Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Glenn Allen Biery, Daniel Mark Boyne, Hormazdyar Minocher Dalal, H. Daniel Schnurmann
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Patent number: 6344234Abstract: A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires.Type: GrantFiled: June 7, 1995Date of Patent: February 5, 2002Assignee: International Business Machines CorportionInventors: Hormazdyar Minocher Dalal, Alexis Bitaillou, Kenneth Michael Fallon, Gene Joseph Gaudenzi, Kenneth Robert Herman, Frederic Pierre, Georges Robert
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Patent number: 6259159Abstract: A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires.Type: GrantFiled: January 30, 1997Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Alexis Bitaillou, Kenneth Michael Fallon, Gene Jospeh Gaudenzi, Kenneth Robert Herman, Frederic Pierre, Georges Robert
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Patent number: 6203926Abstract: A corrosion resistant, multi-layer structure on a substrate including an adhesion metallic layer on the substrate, a cushion metallic layer on the adhesion layer, a diffusion barrier layer on the cushion layer, and an impermeable gold layer that encapsulates all the layers, is substantially even on all sides of the layers, and contacts a region on the substrate adjacent the layers to prevent oxidation and corrosion.Type: GrantFiled: December 28, 1999Date of Patent: March 20, 2001Assignee: International Business Machines CorporationInventors: Umar Moez Uddin Ahmad, Harsaran Singh Bhatia, Satya Pal Singh Bhatia, Hormazdyar Minocher Dalal, William Henry Price, Sampath Purushothaman
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Patent number: 6051273Abstract: A material deposition process is disclosed in which apertures of a contact mask used therein have a constricted opening terminating in a `knife edge` in a sidewall thereof near the top mask side, especially within the top 25% of the mask thickness above the substrate. A process is disclosed in which the mask, in addition, has apertures which have larger dimension lower openings on a bottom side of the mask contacting the substrate than constricted openings near the top side of the mask. Single solder bump and "bump on bump" over BLM (ball limiting metallurgy) processes are disclosed which utilize such contact mask to reduce the damage and detaching of such features during processing and subsequent handling.Type: GrantFiled: November 18, 1997Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Gene Joseph Gaudenzi, Frederic Robert Pierre, Georges Henri Robert
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Patent number: 5976970Abstract: A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang.Type: GrantFiled: March 29, 1996Date of Patent: November 2, 1999Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Hazara Singh Rathore
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Patent number: 5922496Abstract: A material deposition contact mask is disclosed in which apertures formed therein have a larger dimension in lower openings in a bottom side of the mask contacting the substrate than in constricted openings located near the top side of the mask. Apertures of the contact mask have knife edges located within the upper sidewalls thereof, e.g. within the top 25% of the mask thickness above the substrate. A mask is disclosed which, in addition, is thermally compensated to the substrate temperature at which the deposition is performed. Methods for fabricating the mask by differential etching are disclosed.Type: GrantFiled: November 18, 1997Date of Patent: July 13, 1999Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Gene Joseph Gaudenzi, Frederic Robert Pierre, Georges Henri Robert
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Patent number: 5796591Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.Type: GrantFiled: June 7, 1995Date of Patent: August 18, 1998Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Kenneth Michael Fallon