Abstract: A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, via use of a two layer planarization composite, consisting of an underlying, anti-reflective coating, which enhances the flow of an overlying photoresist layer. A two phase, RIE procedure is then employed, with the initial phase exposing thick insulator in narrow shallow trench regions, but leaving the two layer planarization composite protecting the thinner insulator in the wide shallow trenches. The second phase of the RIE procedure removes thick insulator, overlying the narrow shallow trenches, resulting in a planarized topography.