Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anistropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: A method of making improved step metal coverage of semiconductor device using enhanced reflow of phosphosilicate glass by ion implantation of arsenic at low temperature is provided. In one embodiment, the fabrication processing includes implanting arsenic into the phosphosilicate glass and reflowing the ion implanted phosphosilicate glass by heating the phosphosilicate glass to smooth the phosphosiliate glass for allowing a metal interconnection.

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Abstract: A method for the fabrication of submicron devices, without the use of submicron lithography. Vertical "zero undercut" etching techniques are employed, in order to convert the submicron thickness of a deposited thin film conductor layer and a thin film insulation layer into submicron gate widths that can be used in a wide variety of devices, including MOS field effect devices, for example. The conversion is achieved by depositing a thin film conductor layer of submicron thickness across a vertical step between adjacent insulator surfaces, and then vertically etching until the only remaining portion of the conductor layer is that portion adjacent the vertical step. The remaining insulation not covered by conductor is then removed. Thus, an insulated gate is provided having a submicron width approximately equal to the thickness of the conductor layer as initially deposited.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: A method for fabricating a metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment, the fabrication processing includes forming a layer of arsenic doped glass as a multilevel interconnect system insulating layer. In another embodiment, the method includes the formation of a multilevel interconnect system insulating layer which includes the formation of a layer of undoped silicon dioxide as a barrier layer and then forming a layer of arsenic doped glass upon the undoped layer.

Abstract: A metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment a layer of arsenic doped glass replaces the conventional phosphorus doped glass insulation layer. In other embodiments a layer of arsenic doped glass upon an undoped layer of silicon dioxide provides the insulation layer. Slow diffusing source-drain impurities along with these insulation layers provide minimum lateral source-drain diffusion.

Abstract: The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

Abstract: An MOS random access memory cell using the capacitance of a buried P-N junction as the storage element is formed by a process compatable with standard N-channel silicon gate manufacturing methods. The cell is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, a buried, fully implanted charge storage element which also is the source of the cell transistor, self-aligned polysilicon gates, multilayer oxide and a thin film of metallization for interconnections. The vertical stacking of the charge storage and transfer elements and the increase in storage area to cell area ratio with the buried storage area provide a cell with very high packing density.

Abstract: A semiconductor device having a p-n junction characterized by low electric field crowding and a resulting high avalanche breakdown voltage requirement. The semiconductor device is comprised of a semiconductor substrate having impurity atoms of one type and a first surface. A first doped region lies in said substrate at said first surface and has dopant atoms of a type opposite to said one type. A second doped region lies in said substrate at said first surface adjacent the entire perimeter of said first doped region. The second doped region extends laterally away from said first doped region, and has dopant atoms of the same type as and of less density than said dopant atoms of said first doped region.

Abstract: In a microelectronic, metal-oxide-semiconductor dynamic random access memory cell having an MOS capacitance signal storage region, leakage current has been found to have a critical dependence upon the voltage level at which the storage gate is operated (V.sub.STORE). The leakage rate undergoes a sharp transition to a low state below a certain critical V.sub.STORE. This transition is due to the shutting off of the leakage from the periphery and field region around the cell. Consequently, maximum refresh time is achieved by modifying the cell to permit operation of the storage gate below the critical voltage, which may be at or near ground level. For an n-channel cell, permanently shifting the flatband voltage at the silicon-oxide interface of the storage capacitor in the negative direction can generate a potential well for charge storage with a very small V.sub.STORE.

Abstract: Disclosed is a process for constructing an array of memory cells. Each cell is constructed to have a high storage capacity and low leakage current. The cells are formed on a surface of a semiconductor substrate. Each cell has a storage region and an adjacent transfer region. The process forms a deep ion layer and a shallow ion layer in the storage region of each cell. At the storage region-transfer region interface, the deep ion layer lies laterally within the shallow ion layer. In the other portions of the storage region, the deep ion layer extends laterally into adjoining channel stops.

Abstract: Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region.

Abstract: A continuous gate electrode overlies the channel of the CCD and is connected to a uniphase clock pulse source for operation of the CCD. Pairs of gate conductor-insulator-semiconductor regions are defined along the channel. In each pair of regions the surface potential-gate voltage characteristic of one region intersects that of the other region, such that in the OFF condition of a clock pulse the potential well at one region of each pair is deeper than that of the other region; in the ON condition of a clock pulse, this situation is reversed. In this manner, charge packets are propagated along the channel and unidirectionality is achieved by locally implanted potential wells or potential barriers in each of the aforesaid regions.