Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to repeatedly execute a first instruction based on a first field of the first instruction indicating that the first instruction is to be iteratively executed.

Abstract: A processor includes a plurality of execution units. Each of the execution units includes a status register configured to store a value indicative of state of the execution unit. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute. The at least one of the execution units is also configured to interrupt execution of the complex instruction to execute a different instruction, and resume, based on the value stored in the status register, execution of the complex instruction at the point interrupted after execution of the different instruction.

Abstract: A processor includes a plurality of execution units. Each of the execution units includes processing logic configured to process data, and registers accessible by the processing logic. At least one of the execution units is configured to execute a first instruction that causes the at least one execution unit to: route a value from a first register of the registers of one of the execution units to the processing logic of one of the execution units, to process the value in the processing logic to generate a result, and to store the result in a second register of the registers of one of the execution units. At least one of the first register, the second register, and the processing logic are located in a different one of the execution units from the at least one of the execution units.

Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping.

Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.

Abstract: A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Abstract: A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.

Abstract: An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage locations containing sets of predefined system data for different operating conditions of the system assigned to the interrupts coupled to set a system configuration. The system data in the register is defined and stored before receipt of an interrupt. On receipt of an interrupt the system controller transmits a selection signal to the register. The register selects a predefined storage location assigned to the received interrupt. The corresponding system configuration data is used to control system configuration of the embedded microcontroller system, such as allocation of CPU time to virtual CPUs and selection of clock frequency or power voltage for modules.

Abstract: An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.

Abstract: An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage.

Abstract: An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.

Abstract: An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage locations containing sets of predefined system data for different operating conditions of the system assigned to the interrupts coupled to set a system configuration. The system data in the register is defined and stored before receipt of an interrupt. On receipt of an interrupt the system controller transmits a selection signal to the register. The register selects a predefined storage location assigned to the received interrupt. The corresponding system configuration data is used to control system configuration of the embedded microcontroller system, such as allocation of CPU time to virtual CPUs and selection of clock frequency or power voltage for modules.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.

Abstract: An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: A method for generating a pulse width modulated (PWM) signal includes determining a PWM period and/or a pulse width of the pulse width modulated signal by counting the number of clock cycles of a reference clock signal and by switching the pulse width modulated signal when a predetermined number of clock cycles is reached. The reference clock signal comprises clock cycles of at least a first clock period and a second clock period. The first clock period and the second clock period differ by an amount of time, which is substantially smaller than both half of the first clock period and half of the second clock period.

Abstract: A system for processing the measuring signals from a sensor 12, including of a first micro-controller 10 having an input for the sensor data, a first memory 18, 19 and a first processor 16, and a second micro-controller 24 having a second memory 26, 30 and a second processor 27. A bus system 22 is provided that connects the first micro-controller 10 with the second micro-controller 24. The first memory 18, 19 stores data and instructions that are configured so as to be adapted to the sensor 12 and enable the conversion of the signals provided by the sensor 12 into data representing the variable to be measured. The first processor 16 executes the instructions stored in the first memory 18, and transfers the resulting data by way of the bus system 22 to the second micro-controller 24. The second memory 26, 30 stores sensor-independent data and instructions, which enable the processing, by the second microprocessor 27, of the data transferred by the bus system 22, representing the variable to be measured.

Abstract: A circuit relates to phase and frequency-locked loop circuits (PLL and FLL circuits) with a controllable tracking oscillator whose signal phase relationship or frequency, respectively, is influenced by an external parameter, a reference oscillator, as well as a phase or frequency comparator, the output signal of which is used to control the tracking oscillator in such a way that any phase or frequency errors are reduced. A circuit provides for an element for the measurement of the external parameter (such as a microprocessor) which is capable of receiving a signal representing the output signal of the phase or frequency comparator, and convert it into a measurement value that represents the present value of the external parameter. This external parameter can, for example, represent the ambient temperature or the supply voltage of the tracking oscillator.