Patents by Inventor Hosam Haggag
Hosam Haggag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8345488Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: April 6, 2011Date of Patent: January 1, 2013Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Patent number: 8325522Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: December 4, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Patent number: 8315100Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: November 20, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Patent number: 8218370Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: July 10, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Publication number: 20110182126Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Publication number: 20110116324Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Publication number: 20110116319Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Publication number: 20110116318Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Patent number: 7944745Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: February 24, 2010Date of Patent: May 17, 2011Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Patent number: 7903465Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: September 25, 2007Date of Patent: March 8, 2011Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Publication number: 20100149879Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: February 24, 2010Publication date: June 17, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Patent number: 7688627Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: September 25, 2007Date of Patent: March 30, 2010Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Publication number: 20080266959Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: September 25, 2007Publication date: October 30, 2008Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Publication number: 20080266958Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: September 25, 2007Publication date: October 30, 2008Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
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Patent number: 6215698Abstract: Bytes of cells in a Flash electrically-programmable read-only-memory (EPROM) are individually erasable by breaking each row of memory cells into byte-wide segments of memory cells, and utilizing a source access transistor with each segment of memory cells to control the source voltage on each segment of memory cells.Type: GrantFiled: May 30, 2000Date of Patent: April 10, 2001Assignee: National Semiconductor CorporationInventors: Hosam Haggag, Albert Bergemont
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Patent number: 5932873Abstract: A capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.Type: GrantFiled: September 17, 1997Date of Patent: August 3, 1999Assignee: Foveon, Inc.Inventors: Albert Bergemont, Min-Hwa Chi, Hosam Haggag, Carver Mead
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Patent number: 5837574Abstract: A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.Type: GrantFiled: January 29, 1997Date of Patent: November 17, 1998Assignee: National Semiconductor CorporationInventors: Albert Bergemont, Carver A. Mead, Min-hwa Chi, Hosam Haggag
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Patent number: 5587596Abstract: The size of an active pixel sensor cell is reduced by utilizing a single MOS transistor formed in a well to perform the functions conventionally performed by a photogate/photodiode, a sense transistor, and an access transistor. Light energy striking the well varies the potential of the well which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.Type: GrantFiled: September 20, 1995Date of Patent: December 24, 1996Assignee: National Semiconductor CorporationInventors: Min-Hwa Chi, Albert Bergemont, Hosam Haggag
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Patent number: 5576237Abstract: A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.Type: GrantFiled: October 17, 1995Date of Patent: November 19, 1996Assignee: National Semiconductor CorporationInventors: Albert Bergemont, Carver A. Mead, Min-hwa Chi, Hosam Haggag
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Patent number: D774488Type: GrantFiled: September 8, 2014Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Aleksander Magi, Hosam Haggag, Terry Pilsner, Hong W. Wong, Steven Lofland, Mark Gallina