Patents by Inventor Hou-An Su

Hou-An Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965692
    Abstract: A human-machine interaction method for a storage device inside a refrigerator, and a refrigerator are provided. The storage device is arranged in a storage compartment of the refrigerator, and the storage device is provided with an operation panel. An operation surface of the operation panel is provided with a knob module having a display screen, and a touch-sensitive key module. The human-machine interaction method includes: acquiring a startup trigger signal of the operation panel; acquiring an operation instruction received by the knob module and/or the touch-sensitive key module; and making a response to the operation instruction according to a preset interaction solution, and driving the display screen to display a corresponding interface. A user can adjust the functions of the refrigerator through the knob module and the touch-sensitive key module simply and conveniently.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 23, 2024
    Assignees: QINGDAO HAIER REFRIGERATOR CO., LTD., HAIER SMART HOME CO., LTD.
    Inventors: Tao Li, Jianguo Hou, Xiang Fei Su
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Publication number: 20240087861
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Patent number: 11854776
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
  • Publication number: 20230307292
    Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
  • Patent number: 11721662
    Abstract: A method of aligning two wafers during a bonding process includes aligning a first wafer having a plurality of alignment markings with a second wafer having a plurality of alignment markings. The method further includes placing a plurality of flags between the first wafer and the second wafer. The method further includes detecting movement of the plurality of flags with respect to the first wafer and the second wafer using at least one sensor. The method further includes determining whether the wafers remain aligned within an alignment tolerance based on the detected movement of the plurality of flags relative to the first wafer and the second wafer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Tai Shih, Ching-Hou Su, Chyi-Tsong Ni, I-Shi Wang, Jeng-Hao Lin, Kuan-Ming Pan, Jui-Mu Cho, Wun-Kai Tsai
  • Patent number: 11695150
    Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
  • Patent number: 11688633
    Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
  • Publication number: 20220367160
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Patent number: 11488814
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
  • Patent number: 11424566
    Abstract: A high-density connecting device is provided. The high-density connecting device includes a first connecting module and a second connecting module. The first connecting module includes a first casing assembly, a first circuit board, and a first socket connector. The second connecting module includes a second casing assembly, a second circuit board, and a second socket connector. When the first connecting module is mated with the second connecting module, a junction end of the first circuit board and a junction end of the second circuit board are inserted into the first socket connector and the second socket connector, respectively, so that the junction end of the first circuit board and the junction end of the second circuit board are electrically connected to the first socket connector and the second socket connector, respectively.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 23, 2022
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Yen-Cheng Chen, Hou-An Su, Frank Hsu, Yu-Ting Sun, Yong Zhang
  • Publication number: 20220231440
    Abstract: A high-density connecting device is provided. The high-density connecting device includes a first connecting module and a second connecting module. The first connecting module includes a first casing assembly, a first circuit board, and a first socket connector. The second connecting module includes a second casing assembly, a second circuit board, and a second socket connector. When the first connecting module is mated with the second connecting module, a junction end of the first circuit board and a junction end of the second circuit board are inserted into the first socket connector and the second socket connector, respectively, so that the junction end of the first circuit board and the junction end of the second circuit board are electrically connected to the first socket connector and the second socket connector, respectively.
    Type: Application
    Filed: May 20, 2021
    Publication date: July 21, 2022
    Inventors: YEN-CHENG CHEN, HOU-AN SU, FRANK HSU, YU-TING SUN, YONG ZHANG
  • Patent number: 11264763
    Abstract: A connector with a direct locking and a rotational pre-ejection function is provided. The connector includes an insulated body, a plurality of terminals, an inner shell, an outer shell, a snap ring, a plurality of fasteners, an ejector, a first elastic element, and a second elastic element. The outer shell has a cam surface, the ejector has an abutting portion, and the abutting portion is in contact with the cam surface. When the connector and a mating connector are inserted into each other, snap bodies of the fasteners and fastener bodies of the mating connector can be snapped into each other to be directly locked. When the connector and the mating connector are to be separated from each other, the snap bodies of the fasteners and the fastener bodies of the mating connector can be separated from each other to be directly unlocked.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 1, 2022
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Hou-An Su, Yong Zhang, Can-Hui Liang, Yu-Ting Sun
  • Publication number: 20220052485
    Abstract: A connector with a direct locking and a rotational pre-ejection function is provided. The connector includes an insulated body, a plurality of terminals, an inner shell, an outer shell, a snap ring, a plurality of fasteners, an ejector, a first elastic element, and a second elastic element. The outer shell has a cam surface, the ejector has an abutting portion, and the abutting portion is in contact with the cam surface. When the connector and a mating connector are inserted into each other, snap bodies of the fasteners and fastener bodies of the mating connector can be snapped into each other to be directly locked. When the connector and the mating connector are to be separated from each other, the snap bodies of the fasteners and the fastener bodies of the mating connector can be separated from each other to be directly unlocked.
    Type: Application
    Filed: September 29, 2020
    Publication date: February 17, 2022
    Inventors: HOU-AN SU, YONG ZHANG, CAN-HUI LIANG, YU-TING SUN
  • Patent number: 11211301
    Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chunting Wu, Ching-Hou Su, Chih-Pin Wang
  • Publication number: 20210384544
    Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
  • Patent number: 11196218
    Abstract: A connector with a direct locking and a rotational pre-ejection function is provided. The connector includes an insulated body, a plurality of terminals, an inner shell, an outer shell, a fastener, an ejector, a first elastic element, and a second elastic element. A plurality of push blocks are disposed in the outer shell, the ejector has a plurality of slope surfaces, and the push blocks are in contact with the slope surfaces, respectively. When the connector and a mating connector are inserted into each other, snap bodies of the fastener and fastener bodies of the mating connector can be snapped into each other to be directly locked. When the connector and the mating connector are to be separated from each other, the outer shell can be rotated to cause the snap bodies to disengage and to cause the push blocks to rotate while in contact with the sloped surfaces to effect ejector rods to move forwardly to eject the mating connector.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 7, 2021
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Hou-An Su, Frank Hsu, Wen-Feng Xie, Can-Hui Liang, Liang-Ju Liang, Yong Zhang
  • Publication number: 20210343587
    Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
  • Patent number: 11101491
    Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
  • Publication number: 20210249321
    Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Chunting WU, Ching-Hou SU, Chih-Pin WANG