Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract: Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader along the perimeter and having a plurality of electrical pathways, a package substrate located below and spaced from the outer perimeter portion and having a plurality of electrical pathways, a plurality of connection points located between the outer perimeter component and the package substrate to provide connection points coupling the plurality of electrical pathways of the outer perimeter portion to the plurality of electrical pathways in the package substrate, and a cavity formed on the bottom of the heat spreader inside the outer perimeter portion.

Abstract: Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader along the perimeter and having a plurality of electrical pathways, a package substrate located below and spaced from the outer perimeter portion and having a plurality of electrical pathways, a plurality of connection points located between the outer perimeter component and the package substrate to provide connection points coupling the plurality of electrical pathways of the outer perimeter portion to the plurality of electrical pathways in the package substrate, and a cavity formed on the bottom of the heat spreader inside the outer perimeter portion.

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.