Patents by Inventor How-Yu Chen

How-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
    Patent number: 7268024
    Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu
  • Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
    Publication number: 20050093067
    Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
    Type: Application
    Filed: November 29, 2004
    Publication date: May 5, 2005
    Inventors: Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu
  • Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
    Patent number: 6867433
    Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: March 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu
  • Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
    Publication number: 20040217420
    Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 4, 2004
    Inventors: Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu