Abstract: A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the processor address space by distributing I/O segments non-contiguously among successive processor bus pages. Individual I/O address space segments, as may be associated with I/O ports, are protected directly by the processor through the selective enablement of page protection for correspondingly mapped ports.

Abstract: A register distributed across multiple single port adapters allows the system to operate the single port adapters identically to a single multi-port adapter. Each adapter has its own priority logic identical to the logic used on a multi-port adapter to select an individual port. The priority logic on the adapter allows the system to deselect one adapter and select another adapter in one operation. Each adapter has switch settings to allow selective control of individual bits on the system bus, which allows multiple adapters to respond to the processor simultaneously for different ports in the same manner as a multi-port adapter. By replying simultaneously, the system can use the same software to control two different hardware adapter types: single port, or multi-port.

Abstract: A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.