Patents by Inventor Howard Hao
Howard Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11301377Abstract: A memory tile, in a local memory, may be considered to be a unit of memory structure that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure. Multiple memory tiles make up a memory segment. By structuring the memory tiles, and a mapping matrix to the memory tiles, within a memory segment, non-blocking, concurrent write and read accesses to the local memory for multiple requestors may be achieved with relatively high throughput. The accesses may be either row-major or column-major for a two-dimensional memory array.Type: GrantFiled: August 20, 2020Date of Patent: April 12, 2022Assignee: Marvell Rianta Semiconductor ULCInventors: Alan Chi-Lun Wai, Alexandre Zassoko, Howard (Hao) Lu
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Publication number: 20220058126Abstract: A memory tile, in a local memory, may be considered to be a unit of memory structure that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure. Multiple memory tiles make up a memory segment. By structuring the memory tiles, and a mapping matrix to the memory tiles, within a memory segment, non-blocking, concurrent write and read accesses to the local memory for multiple requestors may be achieved with relatively high throughput. The accesses may be either row-major or column-major for a two-dimensional memory array.Type: ApplicationFiled: August 20, 2020Publication date: February 24, 2022Inventors: Alan Chi-Lun Wai, Alexandre ZASSOKO, Howard (Hao) LU
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Patent number: 8832029Abstract: A record of changes to virtual machine data of a virtual machine and a record of changes to snapshots of the virtual machine that have been received since the virtual machine was last backed up are maintained. In response to it being time to perform an incremental backup of the virtual machine, a portion of the virtual machine data is backed up based on the record of changes to the virtual machine data, and a portion of the snapshots is backed up based on the record of changes to the snapshots. In response to it being time to migrate the virtual machine to a second host device, the virtual machine data, the record of changes to the virtual machine data, the record of changes to the snapshots, and one or more of the snapshots are migrated to the second host device.Type: GrantFiled: February 16, 2011Date of Patent: September 9, 2014Assignee: Microsoft CorporationInventors: Angshuman Bezbaruah, Christopher L. Eck, Soumya Kanti Das Bhaumik, Hasan Serdar Sutay, Howard Hao
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Publication number: 20130054533Abstract: The subject disclosure is directed towards verifying a data recovery component of a volume snapshot service using a managed interface. The managed interface enables interoperability between the data recovery component and one or more complementary data recovery components by converting compatible instructions for the data recovery component and a complementary data recovery component into native data recovery operations for the volume snapshot service and vice versa. Via the managed interface, the complementary data recovery component emulates the native data recovery operations. Using status information associated with such an emulation, the data recovery component is verifiable.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: MICROSOFT CORPORATIONInventors: Howard Hao, James Robert Benton, Thothathri Vanamamalai
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Publication number: 20120209812Abstract: A record of changes to virtual machine data of a virtual machine and a record of changes to snapshots of the virtual machine that have been received since the virtual machine was last backed up are maintained. In response to it being time to perform an incremental backup of the virtual machine, a portion of the virtual machine data is backed up based on the record of changes to the virtual machine data, and a portion of the snapshots is backed up based on the record of changes to the snapshots. In response to it being time to migrate the virtual machine to a second host device, the virtual machine data, the record of changes to the virtual machine data, the record of changes to the snapshots, and one or more of the snapshots are migrated to the second host device.Type: ApplicationFiled: February 16, 2011Publication date: August 16, 2012Applicant: MICROSOFT CORPORATIONInventors: Angshuman Bezbaruah, Christopher L. Eck, Soumya Kanti Das Bhaumik, Hasan Serdar Sutay, Howard Hao
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Patent number: 8129609Abstract: Semiconductor integrated thermoelectric devices are provided, which are formed having high-density arrays of thermoelectric (TE) elements using semiconductor thin-film and VLSI (very large scale integration) fabrication processes. Thermoelectric devices can be either separately formed and bonded to semiconductor chips, or integrally formed within the non-active surface of semiconductor chips, for example.Type: GrantFiled: May 13, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Richard C. Chu, Louis L. Hsu
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Patent number: 8004097Abstract: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.Type: GrantFiled: October 2, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis L. Hsu
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Patent number: 7947566Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.Type: GrantFiled: January 31, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis Lu-Chen Hsu, Jack Allan Mandelman
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Patent number: 7867820Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.Type: GrantFiled: May 15, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Howard Hao Chen, Louis L. Hsu, Wolfgang Sauter
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Patent number: 7736949Abstract: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.Type: GrantFiled: August 27, 2008Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis Lu-Chen Hsu
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Publication number: 20090217961Abstract: Semiconductor integrated thermoelectric devices are provided, which are formed having high-density arrays of thermoelectric (TE) elements using semiconductor thin-film and VLSI (very large scale integration) fabrication processes. Thermoelectric devices can be either separately formed and bonded to semiconductor chips, or integrally formed within the non-active surface of semiconductor chips, for example.Type: ApplicationFiled: May 13, 2009Publication date: September 3, 2009Applicant: International Business Machines CorporationInventors: Howard Hao Chen, Richard C. Chu, Louis L. Hsu
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Patent number: 7544883Abstract: Semiconductor integrated thermoelectric devices are provided, which are formed having high-density arrays of thermoelectric (TE) elements using semiconductor thin-film and VLSI (very large scale integration) fabrication processes. Thermoelectric devices can be either separately formed and bonded to semiconductor chips, or integrally formed within the non-active surface of semiconductor chips, for example.Type: GrantFiled: November 12, 2004Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Richard C. Chu, Louis L. Hsu
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Publication number: 20090121312Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.Type: ApplicationFiled: January 31, 2008Publication date: May 14, 2009Inventors: Howard Hao Chen, Louis Lu-Chen Hsu, Jack Allan Mandelman
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Patent number: 7528483Abstract: A cooling system for a semiconductor substrate includes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.Type: GrantFiled: November 9, 2006Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis L. Hsu, Joseph F. Shepard, Jr.
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Patent number: 7489025Abstract: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.Type: GrantFiled: January 4, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis Lu-Chen Hsu
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Publication number: 20090020891Abstract: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.Type: ApplicationFiled: October 2, 2008Publication date: January 22, 2009Inventors: Howard Hao Chen, Louis L. Hsu
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Publication number: 20080318360Abstract: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Inventors: HOWARD HAO CHEN, LOUIS LU-CHEN HSU
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Publication number: 20080280399Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.Type: ApplicationFiled: May 15, 2008Publication date: November 13, 2008Inventors: Lloyd G. Burrell, Howard Hao Chen, Louis L. Hsu, Wolfgang Sauter
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Patent number: 7442579Abstract: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.Type: GrantFiled: November 22, 2004Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis L. Hsu
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Patent number: 7405108Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.Type: GrantFiled: November 20, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Howard Hao Chen, Louis L. Hsu, Wolfgang Sauter