Abstract: Methods and systems consistent with the present invention provide a method for dynamically controlling power consumption in a digital demodulator circuit by varying clock rates and bit widths of demodulator components including an analog to digital converter, decimation filter, OFDM operating engine, FEC decoder, and MPE-FEC processor, according to parameters and conditions of the received signal including modulation mode, signal to noise ratio, effective bit transmission rate, bit error rate, packet error rate, adjacent channel interference, and co-channel interference.

Abstract: An input random access memory (RAM) module of a fast Fourier transform (FFT) engine of a DVB receiver is used to store, during a first time period, delayed versions of an input signal that includes a first orthogonal frequency division multiplexed (OFDM) symbol and a cyclic prefix therefor received at the receiver, and samples for a second OFDM symbol to be demodulated using the FFT engine during a second time period. Delayed versions of the input signal are stored in the input RAM module of the FFT engine in a first-in-first-out (FIFO) fashion for signal acquisition and for FFT processing. Similarly, an output RAM module of the FFT engine is used to store moving averages of an autocorrelation of the input signal with its cyclic prefix computed over presumed guard intervals and over multiple symbols.