Patents by Inventor Howard Tweddle
Howard Tweddle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10283501Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.Type: GrantFiled: March 2, 2017Date of Patent: May 7, 2019Assignee: GaN Systems Inc.Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle
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Patent number: 10249506Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.Type: GrantFiled: September 22, 2017Date of Patent: April 2, 2019Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle
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Publication number: 20180012770Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: Thomas MACELWEE, Greg P. KLOWAK, Howard TWEDDLE
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Patent number: 9818857Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.Type: GrantFiled: October 28, 2014Date of Patent: November 14, 2017Assignee: GaN Systems Inc.Inventors: Greg P. Klowak, Cameron McKnight-Macneil, Howard Tweddle, Ahmad Mizan, Nigel Springett
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Publication number: 20170256638Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.Type: ApplicationFiled: March 2, 2017Publication date: September 7, 2017Inventors: Thomas MACELWEE, Greg P. KLOWAK, Howard TWEDDLE
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Publication number: 20160284829Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.Type: ApplicationFiled: October 28, 2014Publication date: September 29, 2016Inventors: Greg P. KLOWAK, Cameron MCKNIGHT-MACNEIL, Howard TWEDDLE, Ahmad MIZAN, Nigel SPRINGETT
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Patent number: 9153509Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.Type: GrantFiled: December 12, 2014Date of Patent: October 6, 2015Assignee: GaN Systems Inc.Inventors: Gregory P. Klowak, Cameron McKnight-MacNeil, Howard Tweddle, Ahmad Mizan, Nigel Springett
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Publication number: 20150162252Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.Type: ApplicationFiled: December 12, 2014Publication date: June 11, 2015Applicant: GAN SYSTEMS INC.Inventors: Gregory P. KLOWAK, Cameron MCKNIGHT-MACNEIL, Howard TWEDDLE, Ahmad MIZAN, Nigel SPRINGETT
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Patent number: 7839467Abstract: The present invention replaces conventional lighting devices, such as incandescent lamps, fluorescent lamps, and LED lamps, with an integrated electro-luminescent film structure, subdivided into electrically isolated micro-panels. Ideally, the electro-luminescent structure comprises separate red, green and blue micro-panels providing a full range of color adjustment. Alternatively, the electro-luminescent film structure includes stacked groups of layers, in which each group emits a different color and is independently controllable.Type: GrantFiled: October 16, 2009Date of Patent: November 23, 2010Assignee: Group IV Semiconductor Inc.Inventors: Carla Miner, Thomas MacElwee, Stephen Naor, Howard Tweddle
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Publication number: 20100033111Abstract: The present invention replaces the conventional cold cathode fluorescent tubes used in backlighting units of liquid crystal displays with an integrated electro-luminescent film structure, subdivided into electrically isolated micro-panels. Ideally, the electro-luminescent structure comprises separate red, green and blue micro-panels providing full color capabilities. Alternatively, the electro-luminescent film structure includes stacked groups of layers, in which each group emits a different color and is independently controllable.Type: ApplicationFiled: October 16, 2009Publication date: February 11, 2010Inventors: Carla Miner, Thomas MacElwee, Stephen Naor, Howard Tweddle
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Patent number: 7616272Abstract: The present invention replaces the conventional cold cathode fluorescent tubes used in backlighting units of liquid crystal displays with an integrated electro-luminescent film structure, subdivided into electrically isolated micro-panels. Ideally, the electro-luminescent structure comprises separate red, green and blue micro-panels providing full color capabilities. Alternatively, the electro-luminescent film structure includes stacked groups of layers, in which each group emits a different color and is independently controllable.Type: GrantFiled: August 17, 2007Date of Patent: November 10, 2009Assignee: Group IV Semiconductor Inc.Inventors: Carla Miner, Thomas MacElwee, Stephen Naor, Howard Tweddle
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Publication number: 20090046222Abstract: The present invention replaces the conventional cold cathode fluorescent tubes used in backlighting units of liquid crystal displays with an integrated electro-luminescent film structure, subdivided into electrically isolated micro-panels. Ideally, the electro-luminescent structure comprises separate red, green and blue micro-panels providing full color capabilities. Alternatively, the electro-luminescent film structure includes stacked groups of layers, in which each group emits a different color and is independently controllable.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventors: Carla Miner, Thomas MacElwee, Stephen Naor, Howard Tweddle
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Patent number: RE49603Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.Type: GrantFiled: May 7, 2020Date of Patent: August 8, 2023Assignee: GAN SYSTEMS INC.Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle