Abstract: A serial buss processor with detailed description of program branching and register addressing. A mask and branch instruction is utilized to effect a relative program branch of up to N + 1 address locations away from the address of the current or masking branch instruction, where N is the number of bits in the data operand. Register addressing is partly direct and partly indirect. The indirect register address scheme employs a directly addressable register, the contents of which are interpreted by an indirect address generator unit which itself is directly addressable such that a single value in the directly addressable register may be used to point to different registers.