Abstract: A driving system and method for electroluminescent displays which by connecting the electroluminescent elements that have been lighted up to the electroluminescent elements that are to be lighted up causes charge to be shared among the elements, so as to increase the voltage level at the anodes of the electroluminescent elements which are to be lighted up, thereby reducing the power consumption and increasing the response speed.

Abstract: A driving system and method for electroluminescent displays which by connecting the electroluminescent elements that have been lighted up to the electroluminescent elements that are to be lighted up causes charge to be shared among the elements, so as to increase the voltage level at the anodes of the electroluminescent elements which are to be lighted up, thereby reducing the power consumption and increasing the response speed.

Abstract: A circuit capable of providing stable timing clock includes: a step-down clamping circuit, an oscillating circuit, and a voltage potential-conversing circuit. The step-down clamping circuit that step down the input first voltage potential, and clamp to output second voltage, the oscillating circuit is coupled to the clamping circuit and is an oscillating circuit that takes the second voltage as a operating voltage to generate a first timing clock signal, which has a lower voltage potential. The voltage potential-conversing circuit is coupled to the oscillating circuit to convert the first timing clock signal into a second timing clock signal, which has a higher voltage potential. And it is a stable timing clock signal available for other system circuit.

Abstract: A circuit capable of providing stable timing clock includes: a step-down clamping circuit, an oscillating circuit, and a voltage potential-conversing circuit. The step-down clamping circuit that step down the input first voltage potential, and clamp to output second voltage, the oscillating circuit is coupled to the clamping circuit and is an oscillating circuit that takes the second voltage as a operating voltage to generate a first timing clock signal, which has a lower voltage potential. The voltage potential-conversing circuit is coupled to the oscillating circuit to convert the first timing clock signal into a second timing clock signal, which has a higher voltage potential. And it is a stable timing clock signal available for other system circuit.

Abstract: A pulse shaper for integrated service digital network (ISDN) U-interface. The pulse shaper of the present invention includes a couple of control clock generators, a clock-controlled fully differential switched-capacitor integrator, a fully differential sample and hold circuit, and a fully differential line driver/Rauch lowpass filter. The pulse shaper converts four-level 2B1Q digital input code (D0 and D1) to five staircase-type analog waveform by using fully differential switched-capacitor integrator. The sample and hold circuit then eliminates the spikes in the five-stair waveform and improve the signal linearity. The lowpass filter and telephone line driver is utilized to perform the output signal to comply with the waveform specification of ANSI T1 5.3.2.1 and 5.3.2.2.

Abstract: A time acquisition system is disclosed with dual independent frequency and phase lock loops, each containing a dedicated voltage controlled oscillator (VCO). The frequency lock loop (FLL) outputs a frequency bias signal, used for coarse frequency lock-up, only when the difference frequency between the input signal and the FLL VCO is outside a predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Significantly, the frequency bias signal is equal to zero when the difference frequency between the input signal and the FLL VCO is inside the frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. The phase lock loop (PLL) provides a phase bias signal, used for fine tuning lock-up, when the difference frequency between the input signal and the PLL VCO is inside the predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Therefore, there is no interaction between loops during the final phase tuning lock-up.