Abstract: A disposable self-sensing signal test strip includes a test strip body. The test strip body has a detection area and a circuit area. The detection area has a detection circuit. An electrochemical processing unit, a wireless transmission unit, and a power source unit are provided in the circuit area. The detection circuit is electrically connected to the electrochemical processing unit. The electrochemical processing unit sends to the detection circuit a control signal for performing detection. After receiving the control signal, the detection circuit reacts electrochemically with the test sample and sends a feedback signal to the electrochemical processing unit. The electrochemical processing unit converts the feedback signal into a detection parameter signal and sends the detection parameter signal through the wireless transmission unit to a receiving unit. The power source unit supplies electricity to the electrochemical processing unit and the wireless transmission unit.

Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Abstract: A gas sampling bag for gas pH measurement includes a main sampling chamber and an electrochemical test strip accommodating chamber for accommodating an electrochemical test strip. The electrochemical test strip includes a strip body, a working electrode, a pH sensing layer, a reference electrode and a solid water absorption layer. The working electrode has a first part located in a detection area of the strip body. The pH sensing layer is formed on the first part. The reference electrode has a second part located in the detection area. The solid water absorbing layer is formed on the detection area and covers the pH sensing layer and the second part. The solid water absorbing layer is used for absorbing or adsorbing water in the gas sample to form an electrical connection between the first and second parts.

Abstract: A gas sampling bag for gas pH measurement includes a main sampling chamber and an electrochemical test strip accommodating chamber for accommodating an electrochemical test strip. The electrochemical test strip includes a strip body, a working electrode, a pH sensing layer, a reference electrode and a solid water absorption layer. The working electrode has a first part located in a detection area of the strip body. The pH sensing layer is formed on the first part. The reference electrode has a second part located in the detection area. The solid water absorbing layer is formed on the detection area and covers the pH sensing layer and the second part. The solid water absorbing layer is used for absorbing or adsorbing water in the gas sample to form an electrical connection between the first and second parts.

Abstract: A method for detecting Helicobacter pylori using an electrochemical test strip, comprising the following steps: making a subject blow a gas sampling bag to obtain a first gas sample, and use an electrochemical test strip to detect the first gas sample to obtain a pH background data; the subject is allowed to consume urea; making the subject blow a gas sampling bag to obtain a second gas sample, and use an electrochemical test strip to detect the second gas sample to obtain a pH detection data; comparing the pH background data and the pH detection data to determine whether the subject's stomach is infected with Helicobacter pylori.

Abstract: An electrochemical test strip includes a strip body, a working electrode, a pH sensing layer, a reference electrode and a solid water absorption layer. The strip body has a detection area for contact with a gas sample. The working electrode is disposed on the strip body and has a first part located in the detection area. The pH sensing layer is disposed on the first part of the working electrode located in the detection area. The reference electrode is disposed on the strip body and has a second part located in the detection area. The solid water absorption layer is disposed in the detection area and covers the pH sensing layer and the second part. The solid water absorption layer is adapted to absorb or adsorb water in the gas sample in a manner that the first and second parts are electrically connected to each other.

Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.

Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.

Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: In some examples, an electronic device, comprises: a plurality of light emitting diodes (LEDs) arranged into first and second zones; and a driver coupled to the LEDs in the first and second zones, the driver to, in an image scan direction, provide a level of power to the LEDs in the first zone and to the LEDs in the second zone.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.

Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.