Patents by Inventor Hsi-Chang Hsu
Hsi-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187382Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: ApplicationFiled: February 13, 2023Publication date: June 15, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Patent number: 11610850Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Patent number: 11600571Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.Type: GrantFiled: December 17, 2020Date of Patent: March 7, 2023Assignee: Siliconware Precision Industries Co., LtdInventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
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Patent number: 11532528Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.Type: GrantFiled: January 28, 2021Date of Patent: December 20, 2022Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20220181225Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.Type: ApplicationFiled: January 28, 2021Publication date: June 9, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20220173052Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: ApplicationFiled: January 28, 2021Publication date: June 2, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Publication number: 20210104465Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
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Patent number: 10903167Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.Type: GrantFiled: February 26, 2019Date of Patent: January 26, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
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Publication number: 20200203277Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.Type: ApplicationFiled: February 26, 2019Publication date: June 25, 2020Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
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Publication number: 20190109092Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.Type: ApplicationFiled: December 11, 2018Publication date: April 11, 2019Inventors: Rui-Feng Tai, Hsiao-Chun Huang, Chun-Hung Lu, Hsi-Chang Hsu, Shih-Ching Chen
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Patent number: 9607974Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: GrantFiled: November 13, 2015Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Patent number: 9397081Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: October 2, 2015Date of Patent: July 19, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20160141281Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: ApplicationFiled: October 2, 2015Publication date: May 19, 2016Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20160141227Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Publication number: 20160005695Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.Type: ApplicationFiled: August 28, 2014Publication date: January 7, 2016Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Rui-Feng Tai, Hsiao-Chun Huang, Chun-Hung Lu, Hsi-Chang Hsu, Shih-Ching Chen
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Patent number: 9177859Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: August 29, 2013Date of Patent: November 3, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Chip scale package with electronic component received in encapsulant, and fabrication method thereof
Patent number: 9040361Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.Type: GrantFiled: December 2, 2010Date of Patent: May 26, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Chien-Ping Huang, Chun-Chi Ke, Hsin-Yi Liao, Hsi-Chang Hsu -
Publication number: 20140332976Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: ApplicationFiled: August 29, 2013Publication date: November 13, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Patent number: 8828796Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.Type: GrantFiled: November 20, 2013Date of Patent: September 9, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Yuan Chi, Wei-Yu Chen, Hung-Wen Liu, Yan-Heng Chen, Hsi-Chang Hsu
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Publication number: 20140183721Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.Type: ApplicationFiled: March 18, 2013Publication date: July 3, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yan-Heng Chen, Chiang-Cheng Chang, Jung-Pang Huang, Hsi-Chang Hsu, Yan-Yi Liao