Patents by Inventor Hsi-Cheng Chu
Hsi-Cheng Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11050554Abstract: Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.Type: GrantFiled: December 30, 2017Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Naru Sundar, Chih-Jen Chang, Robert Southworth, Hsi-Cheng Chu
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Publication number: 20190044859Abstract: Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.Type: ApplicationFiled: December 30, 2017Publication date: February 7, 2019Inventors: Naru Sundar, Chih-Jen Chang, Robert Southworth, Hsi-Cheng Chu
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Patent number: 9471526Abstract: A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.Type: GrantFiled: November 26, 2013Date of Patent: October 18, 2016Assignee: Marvell World Trade LTD.Inventors: Chun-Lun Lin, Kanting Tsai, Dishi Lai, Hsi-Cheng Chu
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Patent number: 8850169Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 1, 2013Date of Patent: September 30, 2014Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20140082226Abstract: A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.Type: ApplicationFiled: November 26, 2013Publication date: March 20, 2014Applicant: Marvell World Trade LTD.Inventors: Chun-Lun Lin, Kanting Tsai, Dishi Lai, Hsi-Cheng Chu
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Patent number: 8595406Abstract: A system including a first controller configured to communicate with a host via a first interface; a second controller configured to communicate with a storage device via a second interface, where the second interface is different than the first interface; and a bridge module configured to allow the second controller to transfer data between the storage device and the host and to allow the second controller to access memory of the host via the first interface during the transfer.Type: GrantFiled: October 19, 2011Date of Patent: November 26, 2013Assignee: Marvell World Trade Ltd.Inventors: Chun-Lun Lin, Kanting Tsai, Dishi Lai, Hsi-Cheng Chu
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Patent number: 8478972Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: GrantFiled: September 28, 2011Date of Patent: July 2, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu
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Patent number: 8478971Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: December 19, 2011Date of Patent: July 2, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang, Hsi-Cheng Chu
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Patent number: 8473728Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: May 24, 2012Date of Patent: June 25, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8190866Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: January 10, 2011Date of Patent: May 29, 2012Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20120102257Abstract: A system including a first controller configured to communicate with a host via a first interface; a second controller configured to communicate with a storage device via a second interface, where the second interface is different than the first interface; and a bridge module configured to allow the second controller to transfer data between the storage device and the host and to allow the second controller to access memory of the host via the first interface during the transfer.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Inventors: Chun-Lun Lin, Kanting Tsai, Dishi Lai, Hsi-Cheng Chu
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Publication number: 20120066479Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: ApplicationFiled: September 28, 2011Publication date: March 15, 2012Inventors: Jack Kang, Hsi-Cheng Chu
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Patent number: 8082427Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 7, 2010Date of Patent: December 20, 2011Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8032737Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: GrantFiled: August 8, 2007Date of Patent: October 4, 2011Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu
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Patent number: 7870372Abstract: A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a first instruction execution thread and a second interrupt signal line corresponding to a second instruction execution thread. In embodiments, the multi-thread processing device may handle interrupts by providing a shared interrupt service routine for multiple threads or by providing each thread its own unique interrupt service routine.Type: GrantFiled: August 13, 2007Date of Patent: January 11, 2011Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 7757070Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 10, 2007Date of Patent: July 13, 2010Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20080082789Abstract: A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a first instruction execution thread and a second interrupt signal line corresponding to a second instruction execution thread. In embodiments, the multi-thread processing device may handle interrupts by providing a shared interrupt service routine for multiple threads or by providing each thread its own unique interrupt service routine.Type: ApplicationFiled: August 13, 2007Publication date: April 3, 2008Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20080040579Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: ApplicationFiled: August 8, 2007Publication date: February 14, 2008Inventors: Jack Kang, Hsi-Cheng Chu